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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ADC12DJ3200QML-SP slvsdr2 ? november 2018 ADC12DJ3200QML-SP 6.4-gsps, single-channel or 3.2-gsps, dual-channel, 12-bit, rf-sampling analog-to-digital converter (adc) 1 1 features 1 ? adc core: ? 12-bit resolution ? up to 6.4 gsps in single-channel mode ? up to 3.2 gsps in dual-channel mode ? noise floor (no signal, v fs = 1.0 v pp-diff ): ? dual-channel mode: ? 149.5 dbfs/hz ? single-channel mode: ? 152.4 dbfs/hz ? buffered analog inputs with v cmi of 0 v: ? analog input bandwidth ( ? 3 db): 7 ghz ? usable input frequency range: > 10 ghz ? full-scale input voltage (v fs , default): 0.8 v pp ? noiseless aperture delay (t ad ) adjustment: ? precise sampling control: 19-fs step size ? temperature and voltage invariant delays ? easy-to-use synchronization features ? automatic sysref timing calibration ? timestamp for sample marking ? jesd204b subclass-1 compliant interface: ? maximum lane rate: 12.8 gbps ? up to 16 lanes allows reduced lane rate ? digital down-converters in dual-channel mode: ? real output: ddc bypass or 2x decimation ? complex output: 4x, 8x, or 16x decimation ? radiation performance: ? total ionizing dose (tid): 300 krad (si) ? single event latchup (sel): 120 mev-cm 2 /mg ? single event upset (seu) immune registers ? power consumption: 3.0 w 2 applications ? satellite communications (satcom) ? phased array radar, sigint, and elint ? synthetic aperture radar (sar) ? time-of-flight and lidar distance measurement ? rf sampling software-defined radio (sdr) ? spectrometry 3 description the ADC12DJ3200QML-SP device is an rf- sampling, giga-sample, analog-to-digital converter (adc) that can directly sample input frequencies from dc to above 10 ghz. in dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 msps. in single-channel mode, the device can sample up to 6400 msps. programmable tradeoffs in channel count (dual-channel mode) and nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. full-power input bandwidth ( ? 3 db) of 7.0 ghz, with usable frequencies exceeding the ? 3-db point in both dual- and single- channel modes, allows direct rf sampling of l-band, s-band, c-band, and x-band for frequency agile systems. the ADC12DJ3200QML-SP uses a high-speed jesd204b output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. the serial output lanes support up to 12.8 gbps, and can be configured to trade off bit rate and number of lanes. innovative synchronization features, including noiseless aperture delay (t ad ) adjustment and sysref windowing, simplify system design for synthetic aperture radar (sar) and phased-array mimo communications. optional digital down converters (ddcs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only). device information (1) part number package body size (nom) ADC12DJ3200QML-SP fclga (196) 15.00 mm 15.00 mm (1) for all available packages, see the package option addendum at the end of the data sheet. ADC12DJ3200QML-SP measured input bandwidth input frequency (ghz) normalized gain response (db) 0 2 4 6 8 10 -12 -9 -6 -3 0 3 d_bw single channel mode dual channel mode advance information tools & software technical documents ordernow productfolder support &community
2 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 8 6.1 absolute maximum ratings ...................................... 8 6.2 esd ratings .............................................................. 8 6.3 recommended operating conditions ....................... 9 6.4 thermal information .................................................. 9 6.5 electrical characteristics: dc specifications .......... 10 6.6 electrical characteristics: power consumption ...... 12 6.7 electrical characteristics: ac specifications (dual- channel mode) ........................................................ 13 6.8 electrical characteristics: ac specifications (single- channel mode) ........................................................ 16 6.9 timing requirements .............................................. 19 6.10 switching characteristics ...................................... 20 7 detailed description ............................................ 25 7.1 overview ................................................................. 25 7.2 functional block diagram ....................................... 26 7.3 feature description ................................................. 27 7.4 device functional modes ........................................ 49 7.5 programming ........................................................... 68 7.6 register maps ......................................................... 70 8 application and implementation ...................... 119 8.1 application information .......................................... 119 8.2 typical application ............................................... 122 8.3 initialization set up .............................................. 125 9 power supply recommendations .................... 125 9.1 power sequencing ................................................ 126 10 layout ................................................................. 127 10.1 layout guidelines ............................................... 127 10.2 layout example .................................................. 128 11 device and documentation support ............... 131 11.1 device support .................................................. 131 11.2 documentation support ...................................... 131 11.3 receiving notification of documentation updates .................................................................. 131 11.4 community resources ........................................ 132 11.5 trademarks ......................................................... 132 11.6 electrostatic discharge caution .......................... 132 11.7 glossary .............................................................. 132 12 mechanical, packaging, and orderable information ......................................................... 132 4 revision history date revision notes november 2018 * initial release. advance information
3 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions zmx package 196-pad flip chip ceramic lga top view advance information agnd tmstp+ ina+ tmstp- syncse bg ina- da3+ va11 ncoa0 ora0 ncoa1 ora1 da3- da2+ da2- da5+ da1+ da5- da1- clk+ clk- va19 va19 caltrig scs calstat sclk sdi sdo da4+ da0+ da4- da0- db4- db0- db4+ db0+ sysref + tdiode+ tdiode- sysref- inb+ pd ncob1 orb1 ncob0 orb0 inb- db7+ db3+ db5- db1- db5+ db1+ db7- db6+ db3- db2+ db6- db2- ab cd e f g h j k l m 12 11 10 9 8 7 6 5 4 3 2 1 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd va11 va11 va11 va11 va11 va11 va11 va11 va11 vd11 vd11 vd11 vd11 vd11 vd11 vd11 vd11 da7+ da7- da6+ da6- agnd agnd vd11 vd11 vd11 vd11 vd11 vd11 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd va19 va19 va19 va19 va19 va19 va19 va19 va19 va19 va19 va19 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd 14 13 n p
4 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions pin i/o description name no. agnd a1, a3, a6, b1, b3, b4, b6, b6, c6, c7, d4, d5, d6, d7, e4, e5, e6, e7, f1, f4, f5, f6, f7, g2, g4, g5, g6, g7, h2, h4, h5, h6, h7, j1, j4, j5, j6, j7, k4, k5, k6, k7, l4, l5, l6, l7, m6, m7, n1, n3, n4, n5, n6, p1, p3, p6 ? analog supply ground. agnd and dgnd should be directly connected on circuit board. bg a2 o bandgap voltage output. this pin is capable of sourcing 100 a and can drive a load up to 80 pf. see the analog reference voltage section for more details. this pin can be left disconnected if not used. calstat b9 o foreground calibration status output or device alarm output. functionality is programmed through cal_status_sel. this pin can be left disconnected if not used. caltrig a9 i foreground calibration trigger input. this pin is only used if hardware calibration triggering is selected in cal_trig_en, otherwise software triggering is performed using cal_soft_trig. this pin should be tied to gnd if not used. clk+ g1 i device (sampling) clock positive input. the clock signal must be ac coupled to this input. in single-channel mode, the analog input signal is sampled on both rising and falling edges. in dual-channel mode, the analog signal is sampled on the rising edge. this differential input has an internal 100- differential termination and is self-biased to the optimal input common mode voltage. clk- h1 i device (sampling) clock negative input. must be ac coupled. da0+ e14 o high-speed serialized-data output for channel a, lane 0, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da0- f14 o high-speed serialized-data output for channel a, lane 0, negative connection. this pin can be left disconnected if not used. da1+ c14 o high-speed serialized-data output for channel a, lane 1, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da1- d14 o high-speed serialized-data output for channel a, lane 1, negative connection. this pin can be left disconnected if not used. da2+ a12 o high-speed serialized-data output for channel a, lane 2, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da2- a13 o high-speed serialized-data output for channel a, lane 2, negative connection. this pin can be left disconnected if not used. da3+ a10 o high-speed serialized-data output for channel a, lane 3, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da3- a11 o high-speed serialized-data output for channel a, lane 3, negative connection. this pin can be left disconnected if not used. da4+ e13 o high-speed serialized-data output for channel a, lane 4, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da4- f13 o high-speed serialized-data output for channel a, lane 4, negative connection. this pin can be left disconnected if not used. advance information
5 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description name no. da5+ c13 o high-speed serialized-data output for channel a, lane 5, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da5- d13 o high-speed serialized-data output for channel a, lane 5, negative connection. this pin can be left disconnected if not used. da6+ b12 o high-speed serialized-data output for channel a, lane 6, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da6- b13 o high-speed serialized-data output for channel a, lane 6, negative connection. this pin can be left disconnected if not used. da7+ b10 o high-speed serialized-data output for channel a, lane 7, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. da7- b11 o high-speed serialized-data output for channel a, lane 7, negative connection. this pin can be left disconnected if not used. db0+ k14 o high-speed serialized-data output for channel b, lane 0, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db0- j14 o high-speed serialized-data output for channel b, lane 0, negative connection. this pin can be left disconnected if not used. db1+ m14 o high-speed serialized-data output for channel b, lane 1, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db1- l14 o high-speed serialized-data output for channel b, lane 1, negative connection. this pin can be left disconnected if not used. db2+ p12 o high-speed serialized-data output for channel b, lane 2, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db2- p13 o high-speed serialized-data output for channel b, lane 2, negative connection. this pin can be left disconnected if not used. db3+ p10 o high-speed serialized-data output for channel b, lane 3, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db3- p11 o high-speed serialized-data output for channel b, lane 3, negative connection. this pin can be left disconnected if not used. db4+ k13 o high-speed serialized-data output for channel b, lane 4, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db4- j13 o high-speed serialized-data output for channel b, lane 4, negative connection. this pin can be left disconnected if not used. db5+ m13 o high-speed serialized-data output for channel b, lane 5, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db5- l13 o high-speed serialized-data output for channel b, lane 5, negative connection. this pin can be left disconnected if not used. db6+ n12 o high-speed serialized-data output for channel b, lane 6, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db6- n13 o high-speed serialized-data output for channel b, lane 6, negative connection. this pin can be left disconnected if not used. db7+ n10 o high-speed serialized-data output for channel b, lane 7, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. db7- n11 o high-speed serialized-data output for channel b, lane 7, negative connection. this pin can be left disconnected if not used. advance information
6 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description name no. dgnd a14, b14, c8, c9, d8, d9, d10, d11, e8, e9, e10, e11, f8, f9, f10, f11, g8, g9, g10, g11, h8, h9, h10, h11, j8, j9, j10, j11, k8, k9, k10, k11, l8, l9, l10, l11, m8, m9, n9, n14, p14 ? digital supply ground. agnd and dgnd should be directly connected on circuit board. ina+ a4 i channel a analog input positive connection. the differential full-scale input range is determined by the full-scale voltage adjust register. the input common mode voltage should be set to agnd. this input is terminated to ground through a 50- termination resistor. use of ina is recommended for single-channel mode due to optimized performance. this pin can be left disconnected if not used. ina- a5 i channel a analog input negative connection. this input is terminated to ground through a 50- termination resistor. use of ina is recommended for single-channel mode due to optimized performance. this pin can be left disconnected if not used. inb+ p4 i channel b analog input positive connection. the differential full-scale input range is determined by the full-scale voltage adjust register. the input common mode voltage should be set to agnd. this input is terminated to ground through a 50- termination resistor. this pin can be left disconnected if not used. inb- p5 i channel b analog input negative connection. this input is terminated to ground through a 50- termination resistor. this pin can be left disconnected if not used. ncoa0 a7 i nco accumulator selection control lsb for ddc a. ncoa0 and ncoa1 select which nco, of a possible four ncos, is used for digital mixing. the remaining unselected ncos continue to run to maintain phase coherency and can be swapped in by changing the values of ncoa0 and ncoa1. this is an asynchronous input. this pin should be tied to gnd if not used. ncoa1 b7 i nco accumulator selection control msb for ddc a. this pin should be tied to gnd if not used. ncob0 p7 i nco accumulator selection control lsb for ddc b. ncob0 and ncob1 select which nco, of a possible four ncos, is used for digital mixing. the remaining unselected ncos continue to run to maintain phase coherency and can be swapped in by changing the values of ncob0 and ncob1. this is an asynchronous input. this pin should be tied to gnd if not used. ncob1 n7 i nco accumulator selection control msb for ddc b. this pin should be tied to gnd if not used. ora0 a8 o fast overrange detection status for channel a for t0 threshold. when the analog input exceeds the threshold programmed into ovr_t0, this status will go high. the minimum pulse duration is set by ovr_n. this pin can be left disconnected if not used. ora1 b8 o fast overrange detection status for channel a for t1 threshold. when the analog input exceeds the threshold programmed into ovr_t1, this status will go high. the minimum pulse duration is set by ovr_n. this pin can be left disconnected if not used. orb0 p8 o fast overrange detection status for channel b for t0 threshold. when the analog input exceeds the threshold programmed into ovr_t0, this status will go high. the minimum pulse duration is set by ovr_n. this pin can be left disconnected if not used. orb1 n8 o fast overrange detection status for channel b for t1 threshold. when the analog input exceeds the threshold programmed into ovr_t1, this status will go high. the minimum pulse duration is set by ovr_n. this pin can be left disconnected if not used. pd p9 i this pin disables all analog circuits and serializer outputs when set high for temperature diode calibration only. do not use this pin to power down the device for power savings. tie this pin to gnd during normal operation. for information regarding reliable serializer operation, see the power-down modes section. advance information
7 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description name no. sclk g14 i serial interface clock. this pin functions as the serial-interface clock input which clocks the serial programming data in and out. using the serial interface describes the serial interface in more detail. supports 1.1 v and 1.8 v cmos levels. scs g13 i serial interface chip select active low input. using the serial interface describes the serial interface in more detail. supports 1.1 v and 1.8 v cmos levels. this pin has a 82-k pull-up resistor to vd11. sdi h13 i serial interface data input. using the serial interface describes the serial interface in more detail. supports 1.1 v and 1.8 v cmos levels. sdo h14 o serial interface data output. using the serial interface describes the serial interface in more detail. this pin is high impedance during normal device operation. this pin outputs 1.9-v cmos levels during serial interface read operations. this pin can be left disconnected if not used. syncse b2 i jesd204b sync signal single-ended active low input. this pin provides the jesd204b- required synchronization request input. a logic low applied to this input initiates code group synchronization and the initial lane alignment sequence. the choice of single-ended or differential sync (using tmstp+ and tmstp- pins) is selected by programming sync_sel. this pin should be tied to gnd if differential sync (tmstp ) is as the jesd204b sync signal. sysref+ l1 i sysref positive input used to achieve synchronization and deterministic latency across the jesd204b interface. this differential input (sysref+ to sysref ? ) has an internal 100- differential termination. it is self-biased when ac coupled (sysref_lvpecl_en must be set to 0), but can be dc coupled by setting sysref_lvpecl_en to 1, which changes the internal termination to 50- single-ended termination to ground on each sysref+ and sysref- input. the common mode voltage must be within the recommended range when dc coupled. sysref- m1 i sysref negative input. tdiode+ n2 i temperature diode positive (anode) connection. an external temperature sensor can be connected to tdiode+ and tdiode- to monitor the junction temperature of the device. this pin can be left disconnected if not used. tdiode- p2 i temperature diode negative (cathode) connection. this pin can be left disconnected if not used. tmstp+ c1 i timestamp input positive connection or differential jesd204b sync positive connection. this input is used as the timestamp input when sync_sel is set to use syncse as the jesd204b sync signal. this input is used as the jesd204b sync signal when sync_sel is set to use tmstp+ and tmstp- as the jesd204b sync signal. for additional usage information as timestamp input, see the timestamp section. this pin can be left disconnected if syncse is used and timestamp is not required. tmstp- d1 i timestamp input positive connection or differential jesd204b sync negative connection. this pin can be left disconnected if syncse is used and timestamp is not required. va11 d3, e3, f2, f3, g3, h3, j2, j3, k3, l3 i 1.1-v analog supply. va19 c2, c3, c4, c5, d2, e1, e2, k1, k2, l2, m2, m3, m4, m5 i 1.9-v analog supply. vd11 c10, c11, c12, d12, e12, f12, g12, h12, j12, k12, l12, m10, m11, m12 i 1.1-v digital supply. advance information
8 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) measured to agnd. (3) measured to dgnd. (4) maximum voltage not to exceed vd11 absolute maximum rating. (5) maximum voltage not to exceed va11 absolute maximum rating. (6) maximum voltage not to exceed va19 absolute maximum rating. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range va19 (2) ? 0.3 2.35 v va11 (2) ? 0.3 1.32 vd11 (3) ? 0.3 1.32 voltage between vd11 and va11 ? 1.32 1.32 voltage between agnd and dgnd ? 0.1 0.1 v pin voltage range da[7:0]+, da[7:0] ? , db[7:0]+, db[7:0] ? , tmstp+, tmstp ? (3) ? 0.5 vd11 + 0.5 (4) v clk+, clk ? , sysref+, sysref ? (2) ? 0.5 va11 + 0.5 (5) bg, tdiode+, tdiode ? (2) ? 0.5 va19 + 0.5 (6) ina+, ina ? , inb+, inb ? (2) ? 1 1 calstat, caltrig, ncoa0, ncoa1, ncob0, ncob1, ora0, ora1, orb0, orb1, pd, sclk, scs, sdi, sdo, syncse (2) ? 0.5 va19 + 0.5 (6) peak input current (any input except ina+, ina ? , inb+, inb ? ) ? 25 25 ma peak input current (ina+, ina ? , inb+, inb ? ) ? 50 50 ma peak rf input power (ina+, ina ? , inb+, inb ? ) single-ended with z s-se = 50 or differential with z s-diff = 100 16.4 dbm peak total input current (sum of absolute value of all currents forced in or out, not including power-supply current) 100 ma junction temperature, t j 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2500 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 500 advance information
9 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) measured to agnd. (2) measured to dgnd. (3) ti strongly recommends that clk be ac-coupled with devclk_lvpecl_en set to 0 to allow clk to self bias to the optimal input common-mode voltage for best performance. ti recommends ac-coupling for sysref unless dc-coupling is required, in which case lvpecl input mode must be used (sysref_lvpecl_en = 1). (4) tmstp does not have internal biasing, which requires tmstp to be biased externally whether ac-coupled with tmstp_lvpecl_en = 0 or dc-coupled with tmstp_lvpecl_en = 1. (5) adc output code saturates when v id for ina or inb exceeds the programmed full-scale voltage (v fs ) set by fs_range_a for ina or fs_range_b for inb . (6) prolonged use above a junction temperature of 105 c may increase the device failure-in-time (fit) rate. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v dd supply voltage range va19, analog 1.9-v supply (1) 1.8 1.9 2.0 v va11, analog 1.1-v supply (1) 1.05 1.1 1.15 vd11, digital 1.1-v supply (2) 1.05 1.1 1.15 v cmi input common-mode voltage ina+, ina ? , inb+, inb ? (1) ? 50 0 100 mv clk+, clk ? , sysref+, sysref ? (1) (3) 0 0.3 0.55 v tmstp+, tmstp ? (2) (4) 0 0.3 0.55 v id input voltage, peak-to-peak differential clk+ to clk ? , sysref+ to sysref ? , tmstp+ to tmstp ? 0.4 1.0 2.0 v pp-diff ina+ to ina ? , inb+ to inb ? 1.0 (5) v ih high-level input voltage caltrig, ncoa0, ncoa1, ncob0, ncob1, pd, sclk, scs, sdi, syncse (1) 0.7 v v il low-level input voltage caltrig, ncoa0, ncoa1, ncob0, ncob1, pd, sclk, scs, sdi, syncse (1) 0.45 v i c_td temperature diode input current tdiode+ to tdiode ? 100 a c l bg maximum load capacitance 100 pf i o bg maximum output current 100 a dc input clock duty cycle 30% 50% 70% t a operating free-air temperature ? 55 o c t j operating junction temperature 125 (6) o c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) ADC12DJ3200QML-SP unit zmx (fclga) 196 pins r ja junction-to-ambient thermal resistance 24.7 c/w r jc(top) junction-to-case (top) thermal resistance 16.5 c/w r jb junction-to-board thermal resistance 10.5 c/w jt junction-to-top characterization parameter 7.5 c/w jb junction-to-board characterization parameter 10.6 c/w r jc(bot) junction-to-case (bottom) thermal resistance 6.5 c/w advance information
10 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for subgroup definitions, please see table 1 . 6.5 electrical characteristics: dc specifications typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit dc accuracy resolution resolution with no missing codes 12 bits dnl differential nonlinearity maximum positive excursion from ideal step size 0.4 lsb maximum negative excursion from ideal step size ? 0.3 lsb inl integral nonlinearity maximum positive excursion from ideal transfer function 3 lsb maximum negative excursion from ideal transfer function ? 2 lsb analog inputs (ina+, ina ? , inb+, inb ? ) v off offset error cal_os = 0 2.0 mv cal_os = 1 0.3 mv v off_adj input offset voltage adjustment range available offset correction range (see cal_os bit in the cal_cfg0 register or the oadj_a_fg0_vina register) 55 mv v off_drift offset drift foreground calibration at nominal temperature only 23 v/ c foreground calibration at each temperature 0 v in_fsr analog differential input full-scale range default full-scale voltage (fs_range_a = fs_range_b = 0xa000) [1, 2, 3] 750 810 850 mv pp maximum full-scale voltage (fs_range_a = fs_range_b = 0xffff) [1, 2, 3] 980 1050 minimum full-scale voltage (fs_range_a = fs_range_b = 0x2000) [1, 2, 3] 490 580 v in_fsr_drift analog differential input full-scale range drift default fs_range_a and fs_range_b setting, foreground calibration at nominal temperature only, inputs driven by 50- source, includes effect of r in drift ? 0.01 %/ c default fs_range_a and fs_range_b setting, foreground calibration at each temperature, inputs driven by 50- source, includes effect of r in drift 0.03 v in_fsr_match analog differential input full-scale range matching matching between ina and inb , default setting, dual-channel mode 0.625% r in single-ended input resistance to agnd each input pin is terminated to agnd, measured at t a = 25 c [1] 48 50 52 r in_tempco input termination linear temperature coefficient 17.6 m / c c in single-ended input capacitance single-channel mode at dc 0.4 pf dual-channel mode at dc 0.4 advance information
11 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: dc specifications (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit temperature diode characteristics (tdiode+, tdiode ? ) v be temperature diode voltage slope forced forward current of 100 a; offset voltage (approximately 0.792 v at 0 c) varies with process and must be measured for each device; perform offset measurement with the device unpowered or with the pd pin asserted to minimize device self- heating; only assert the pd pin long enough to take the offset measurement ? 1.6 mv/ c band-gap voltage output (bg) v bg reference output voltage i l 100 a 1.1 v v bg_drift reference output temperature drift i l 100 a ? 64 v/ c clock inputs (clk+, clk ? , sysref+, sysref ? , tmstp+, tmstp ? ) z t internal termination differential termination with devclk_lvpecl_en = 0, sysref_lvpecl_en = 0, and tmstp_lvpecl_en = 0 [1] 100 single-ended termination to gnd (per pin) with devclk_lvpecl_en = 0, sysref_lvpecl_en = 0, and tmstp_lvpecl_en = 0 50 v cm input common-mode voltage, self-biased self-biasing common-mode voltage for clk when ac-coupled (devclk_lvpecl_en must be set to 0) 0.3 v self-biasing common-mode voltage for sysref when ac-coupled (sysref_lvpecl_en must be set to 0) and with receiver enabled (sysref_recv_en = 1) 0.3 self-biasing common-mode voltage for sysref when ac-coupled (sysref_lvpecl_en must be set to 0) and with receiver disabled (sysref_recv_en = 0) va11 c l_diff differential input capacitance between positive and negative differential input pins 0.1 pf c l_se single-ended input capacitance each input to ground 0.5 pf serdes outputs (da[7:0]+, da[7:0] ? , db[7:0]+, db[7:0] ? ) v od differential output voltage, peak-to-peak 100- load [1, 2, 3] 500 600 700 mv pp- diff v cm output common-mode voltage ac-coupled vd11 / 2 v z diff differential output impedance 100 advance information
12 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: dc specifications (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit cmos interface (sclk, sdi, sdo, scs, pd, ncoa0, ncoa1, ncob0, ncob1, calstat, caltrig, ora0, ora1, orb0, orb1, syncse) i ih high-level input current [1, 2, 3] 40 a i il low-level input current [1, 2, 3] ? 40 a c i input capacitance 2 pf v oh high-level output voltage i load = ? 400 a [1, 2, 3] 1.65 v v ol low-level output voltage i load = 400 a [1, 2, 3] 150 mv (1) for subgroup definitions, please see table 1 . 6.6 electrical characteristics: power consumption typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit i va19 1.9-v analog supply current power mode 1: single-channel mode, jmode 1 (16 lanes, ddc bypassed), foreground calibration 890 ma i va11 1.1-v analog supply current 500 ma i vd11 1.1-v digital supply current 542 ma p dis power dissipation 2.8 w i va19 1.9-v analog supply current power mode 2: single-channel mode, jmode 0 (8 lanes, ddc bypassed), foreground calibration [1, 2, 3] 890 ma i va11 1.1-v analog supply current [1, 2, 3] 500 ma i vd11 1.1-v digital supply current [1, 2, 3] 595 ma p dis power dissipation [1, 2, 3] 2.9 w i va19 1.9-v analog supply current power mode 3: single-channel mode, jmode 1 (16 lanes, ddc bypassed), background calibration 1172 ma i va11 1.1-v analog supply current 600 ma i vd11 1.1-v digital supply current 561 ma p dis power dissipation 3.5 w i va19 1.9-v analog supply current power mode 4: dual-channel mode, jmode 3 (16 lanes, ddc bypassed), background calibration 1254 ma i va11 1.1-v analog supply current 600 ma i vd11 1.1-v digital supply current 573 ma p dis power dissipation 3.7 w i va19 1.9-v analog supply current power mode 5: dual-channel mode, jmode 11 (8 lanes, 4x decimation), foreground calibration 971 ma i va11 1.1-v analog supply current 500 ma i vd11 1.1-v digital supply current 1098 ma p dis power dissipation 3.7 w advance information
13 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for subgroup definitions, please see table 1 . (2) full-power input bandwidth (fpbw) is defined as the input frequency where the reconstructed output of the adc has dropped 3 db below the power of a full-scale input signal at a low input frequency. useable bandwidth may exceed the ? 3-db full-power input bandwidth. 6.7 electrical characteristics: ac specifications (dual-channel mode) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit fpbw full-power input bandwidth ( ? 3 db) (2) foreground calibration 7.3 ghz background calibration 7.3 xtalk channel-to-channel crosstalk dual-channel mode, aggressor = 400 mhz, ? 1 dbfs ? 86 db dual-channel mode, aggressor = 3 ghz, ? 1 dbfs ? 58 dual-channel mode, aggressor = 6 ghz, ? 1 dbfs ? 59 cer code error rate does not include serdes bit-error rate (ber) 10 ? 18 errors / sample noise dc dc input noise standard deviation no input, foreground calibration, excludes dc offset, includes fixed interleaving spur (f s / 2 spur) 2.5 lsb nsd noise spectral density, no input signal, excludes fixed interleaving spur (f s / 2 spur) maximum full-scale voltage (fs_range_a = fs_range_b = 0xffff) setting, foreground calibration ? 149.5 dbfs/hz default full-scale voltage (fs_range_a = fs_range_b = 0xa000) setting, foreground calibration ? 147.5 nf noise figure, no input, z s = 100 maximum full-scale voltage (fs_range_a = 0xffff) setting, foreground calibration 23.5 db default full-scale voltage (fs_range_a = 0xa000) setting, foreground calibration 25.5 snr signal-to-noise ratio, large signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 1 dbfs 56 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 57.0 f in = 997 mhz, a in = ? 1 dbfs 55.7 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 55 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 55.8 f in = 4997 mhz, a in = ? 1 dbfs 52.5 f in = 6397 mhz, a in = ? 1 dbfs 51.5 f in = 8197 mhz, a in = ? 1 dbfs 50 snr signal-to-noise ratio, small signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 16 dbfs 56 dbfs f in = 997 mhz, a in = ? 16 dbfs 56 f in = 2482 mhz, a in = ? 16 dbfs 56 f in = 4997 mhz, a in = ? 16 dbfs 56 f in = 6397 mhz, a in = ? 16 dbfs 56 f in = 8197 mhz, a in = ? 16 dbfs 56 advance information
14 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: ac specifications (dual-channel mode) (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit sinad signal-to-noise and distortion ratio, large signal, excluding dc and f s / 2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 55.8 dbfs f in = 997 mhz, a in = ? 1 dbfs 55.5 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 54.5 f in = 4997 mhz, a in = ? 1 dbfs 50.5 f in = 6397 mhz, a in = ? 1 dbfs 49.5 f in = 8197 mhz, a in = ? 1 dbfs 47 enob effective number of bits, large signal, excluding dc and f s / 2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 9.0 bits f in = 997 mhz, a in = ? 1 dbfs 8.9 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 8.8 f in = 4997 mhz, a in = ? 1 dbfs 8.1 f in = 6397 mhz, a in = ? 1 dbfs 7.9 f in = 8197 mhz, a in = ? 1 dbfs 7.5 sfdr spurious-free dynamic range, large signal, excluding dc and f s / 2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 68 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 67 f in = 997 mhz, a in = ? 1 dbfs 67 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 66 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 62 f in = 4997 mhz, a in = ? 1 dbfs 59 f in = 6397 mhz, a in = ? 1 dbfs 57 f in = 8197 mhz, a in = ? 1 dbfs 53 sfdr spurious-free dynamic range, small signal, excluding dc and f s / 2 fixed spurs f in = 347 mhz, a in = ? 16 dbfs 73 dbfs f in = 997 mhz, a in = ? 16 dbfs 74 f in = 2482 mhz, a in = ? 16 dbfs 73 f in = 4997 mhz, a in = ? 16 dbfs 73 f in = 6397 mhz, a in = ? 16 dbfs 74 f in = 8197 mhz, a in = ? 16 dbfs 73 f s / 2 f s / 2 fixed interleaving spur, independent of input signal no input [4, 5, 6] ? 77 dbfs hd2 2nd-order harmonic distortion f in = 347 mhz, a in = ? 1 dbfs ? 74 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 77 f in = 997 mhz, a in = ? 1 dbfs ? 74 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 74 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 72 f in = 4997 mhz, a in = ? 1 dbfs ? 61 f in = 6397 mhz, a in = ? 1 dbfs ? 64 f in = 8197 mhz, a in = ? 1 dbfs ? 63 advance information
15 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: ac specifications (dual-channel mode) (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit hd3 3rd-order harmonic distortion f in = 347 mhz, a in = ? 1 dbfs ? 72 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 68 f in = 997 mhz, a in = ? 1 dbfs ? 72 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 66 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 62 f in = 4997 mhz, a in = ? 1 dbfs ? 59 f in = 6397 mhz, a in = ? 1 dbfs ? 57 f in = 8197 mhz, a in = ? 1 dbfs ? 53 f s / 2-f in f s / 2 ? f in interleaving spur, signal dependent f in = 347 mhz, a in = ? 1 dbfs ? 70 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 74 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 74 f in = 4997 mhz, a in = ? 1 dbfs ? 71 f in = 6397 mhz, a in = ? 1 dbfs ? 68 f in = 8197 mhz, a in = ? 1 dbfs ? 69 spur worst-harmonic, 4th-order distortion or higher f in = 347 mhz, a in = ? 1 dbfs ? 75 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 73 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 72 f in = 4997 mhz, a in = ? 1 dbfs ? 69 f in = 6397 mhz, a in = ? 1 dbfs ? 68 f in = 8197 mhz, a in = ? 1 dbfs ? 66 imd3 3rd-order intermodulation distortion f in = 347 mhz 5 mhz, a in = ? 7 dbfs per tone ? 86 dbfs f in = 997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 82 f in = 2482 mhz 5 mhz, a in = ? 7 dbfs per tone ? 73 f in = 4997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 65 f in = 6397 mhz 5 mhz, a in = ? 7 dbfs per tone ? 60 f in = 8197 mhz 5 mhz, a in = ? 7 dbfs per tone ? 52 advance information
16 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for subgroup definitions, please see table 1 . (2) full-power input bandwidth (fpbw) is defined as the input frequency where the reconstructed output of the adc has dropped 3 db below the power of a full-scale input signal at a low input frequency. useable bandwidth may exceed the ? 3-db full-power input bandwidth. 6.8 electrical characteristics: ac specifications (single-channel mode) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina , f in = 248 mhz, a in = ? 1 dbfs,f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit fpbw full-power input bandwidth ( ? 3 db) (2) foreground calibration 7.1 ghz background calibration 7.1 cer code error rate does not include serdes bit-error rate (ber) 10 ? 18 errors / sample noise dc dc input noise standard deviation no input, foreground calibration, excludes dc offset, includes fixed interleaving spurs (f s / 2 and f s / 4 spurs) 2.8 lsb nsd noise spectral density, no input signal, excludes fixed interleaving spurs (f s / 2 and f s / 4 spur) maximum full-scale voltage (fs_range_a = 0xffff) setting, foreground calibration ? 152.4 dbfs/hz default full-scale voltage (fs_range_a = 0xa000) setting, foreground calibration ? 150.0 nf noise figure, no input, z s = 100 maximum full-scale voltage (fs_range_a = 0xffff) setting, foreground calibration 20.6 db default full-scale voltage (fs_range_a = 0xa000) setting, foreground calibration 23.1 snr signal-to-noise ratio, large signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 1 dbfs 56 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 57 f in = 997 mhz, a in = ? 1 dbfs 55.7 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 55 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 56 f in = 4997 mhz, a in = ? 1 dbfs 52.5 f in = 6397 mhz, a in = ? 1 dbfs 51.5 f in = 8197 mhz, a in = ? 1 dbfs 50.0 snr signal-to-noise ratio, small signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 16 dbfs 56 dbfs f in = 997 mhz, a in = ? 16 dbfs 56 f in = 2482 mhz, a in = ? 16 dbfs 56 f in = 4997 mhz, a in = ? 16 dbfs 55.8 f in = 6397 mhz, a in = ? 16 dbfs 55.7 f in = 8197 mhz, a in = ? 16 dbfs 55.8 sinad signal-to-noise and distortion ratio, large signal, excluding dc and f s / 2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 53.5 dbfs f in = 997 mhz, a in = ? 1 dbfs 52.7 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 52.1 f in = 4997 mhz, a in = ? 1 dbfs 50 f in = 6397 mhz, a in = ? 1 dbfs 48.8 f in = 8197 mhz, a in = ? 1 dbfs 46 advance information
17 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: ac specifications (single-channel mode) (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina , f in = 248 mhz, a in = ? 1 dbfs,f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit enob effective number of bits, large signal, excluding dc and f s / 2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 8.6 bits f in = 997 mhz, a in = ? 1 dbfs 8.5 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 8.4 f in = 4997 mhz, a in = ? 1 dbfs 8.0 f in = 6397 mhz, a in = ? 1 dbfs 7.8 f in = 8197 mhz, a in = ? 1 dbfs 7.3 sfdr spurious-free dynamic range, large signal, excluding dc, f s / 4 and f s / 2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 64 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 65 f in = 997 mhz, a in = ? 1 dbfs 61 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] 55 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 52 f in = 4997 mhz, a in = ? 1 dbfs 57 f in = 6397 mhz, a in = ? 1 dbfs 56 f in = 8197 mhz, a in = ? 1 dbfs 50 sfdr spurious-free dynamic range, small signal, excluding dc, f s / 4 and f s / 2 fixed spurs f in = 347 mhz, a in = ? 16 dbfs 68 dbfs f in = 997 mhz, a in = ? 16 dbfs 66 f in = 2482 mhz, a in = ? 16 dbfs 65 f in = 4997 mhz, a in = ? 16 dbfs 66 f in = 6397 mhz, a in = ? 16 dbfs 67 f in = 8197 mhz, a in = ? 16 dbfs 63 f s / 2 f s / 2 fixed interleaving spur, independent of input signal no input, os_cal disabled, spur can be improved by running os_cal ? 65 dbfs f s / 4 f s / 4 fixed interleaving spur, independent of input signal no input [4, 5, 6] ? 67 dbfs hd2 2nd-order harmonic distortion f in = 347 mhz, a in = ? 1 dbfs ? 70 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 70 f in = 997 mhz, a in = ? 1 dbfs ? 73 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 75 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 75 f in = 4997 mhz, a in = ? 1 dbfs ? 64 f in = 6397 mhz, a in = ? 1 dbfs ? 68 f in = 8197 mhz, a in = ? 1 dbfs ? 66 advance information
18 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: ac specifications (single-channel mode) (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina , f in = 248 mhz, a in = ? 1 dbfs,f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit hd3 3rd-order harmonic distortion f in = 347 mhz, a in = ? 1 dbfs ? 71 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 69 f in = 997 mhz, a in = ? 1 dbfs ? 70 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 67 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 63 f in = 4997 mhz, a in = ? 1 dbfs ? 61 f in = 6397 mhz, a in = ? 1 dbfs ? 60 f in = 8197 mhz, a in = ? 1 dbfs ? 56 f s / 2-f in f s / 2 ? f in interleaving spur, signal dependent f in = 347 mhz, a in = ? 1 dbfs ? 66 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 62 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 55 f in = 4997 mhz, a in = ? 1 dbfs ? 58 f in = 6397 mhz, a in = ? 1 dbfs ? 57 f in = 8197 mhz, a in = ? 1 dbfs ? 51 f s / 4 f in f s / 4 f in interleaving spurs, signal dependent f in = 347 mhz, a in = ? 1 dbfs ? 76 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 75 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 74 f in = 4997 mhz, a in = ? 1 dbfs ? 71 f in = 6397 mhz, a in = ? 1 dbfs ? 69 f in = 8197 mhz, a in = ? 1 dbfs ? 67 spur worst harmonic 4th-order distortion or higher f in = 347 mhz, a in = ? 1 dbfs ? 73 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 73 f in = 2482 mhz, a in = ? 1 dbfs [4, 5, 6] ? 72 f in = 4997 mhz, a in = ? 1 dbfs ? 68 f in = 6397 mhz, a in = ? 1 dbfs ? 67 f in = 8197 mhz, a in = ? 1 dbfs ? 65 imd3 3rd-order intermodulation distortion f in = 347 mhz 5 mhz, a in = ? 7 dbfs per tone ? 89 dbfs f in = 997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 79 f in = 2482 mhz 5 mhz, a in = ? 7 dbfs per tone ? 73 f in = 4997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 65 f in = 6397 mhz 5 mhz, a in = ? 7 dbfs per tone ? 61 f in = 8197 mhz 5 mhz, a in = ? 7 dbfs per tone ? 54 advance information
19 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for subgroup definitions, please see table 1 . (2) unless functionally limited to a smaller range in table 19 based on the programmed jmode. (3) use sysref_pos to select an optimal sysref_sel value for sysref capture, see sysref position detector and sampling position selection (sysref windowing) for more information on sysref windowing. the invalid region, specified by t inv(sysref) , indicates the portion of the clk period (t clk ), as measured by sysref_sel, that may result in a setup and hold violation. verify that the timing skew between sysref and clk over system operating conditions from the nominal conditions (that used to find optimal sysref_sel) does not result in the invalid region occurring at the selected sysref_sel position in sysref_pos, otherwise a temperature dependent sysref_sel selection may be needed to track the skew between clk and sysref . 6.9 timing requirements subgroup (1) min nom max unit device (sampling) clock (clk+, clk ? ) f clk input clock frequency (clk+, clk ? ), both single-channel and dual-channel modes (2) maximum input clock frequency [4, 5, 6] 3200 mhz minimum input clock frequency 800 mhz sysref (sysref+, sysref ? ) t clk input clock period (clk+, clk ? ), both single- channel and dual-channel modes (2) maximum input clock frequency [4, 5, 6] 312. 5 ps minimum input clock frequency 1250 ps t inv(sysref) duration of invalid sysref capture region of clk period, indicating setup or hold time violation, as measured by the sysref_pos status register (3) 48 ps t inv(temp) drift of invalid sysref capture region over temperature, a positive number indicates a shift toward the msb of the sysref_pos register 0 ps/ c t inv(va11) drift of invalid sysref capture region over the va11 supply voltage, a positive number indicates a shift toward the msb of the sysref_pos register 0.36 ps/mv t step(sp) delay of the sysref_pos lsb sysref_zoom = 0 77 ps sysref_zoom = 1 24 t (ph_sys) minimum sysref assertion duration after a sysref rising edge event 4 ns t (pl_sys) minimum sysref de-assertion duration after a sysref falling edge event 4 ns jesd204b sync timing ( syncse or tmstp ) t h( syncse) minimum hold time from multiframe boundary (sysref rising edge captured high) to de- assertion of jesd204b sync signal ( syncse if sync_sel = 0 or tmstp if sync_sel = 1) for nco synchronization (nco_sync_ila = 1) jmode = 0, 2, 4, 6, 10, 13 or 15 21 t clk cycles jmode = 1, 3, 5, 7, 9, 11, 14 or 16 17 jmode = 12, 17 or 18 9 t su( syncse) minimum setup time from de-assertion of jesd204b sync signal ( syncse if sync_sel = 0 or tmstp if sync_sel = 1) to multiframe boundary (sysref rising edge captured high) for nco synchronization (nco_sync_ila = 1) jmode = 0, 2, 4, 6, 10, 13 or 15 ? 2 t clk cycles jmode = 1, 3, 5, 7, 9, 11, 14 or 16 2 jmode = 12, 17 or 18 10 t ( syncse) syncse minimum assertion time to trigger link resynchronization 4 frames serial programming interface (sclk, sdi, scs) f clk(sclk) serial clock frequency 0 15.6 25 mhz t (ph) serial clock high value pulse duration 32 ns t (pl) serial clock low value pulse duration 32 ns t su( scs) setup time from scs to rising edge of sclk 25 ns t h( scs) hold time from rising edge of sclk to scs 3 ns t su(sdi) setup time from sdi to rising edge of sclk 25 ns t h(sdi) hold time from rising edge of sclk to sdi 3 ns advance information
20 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for subgroup definitions, please see table 1 . (2) t aj increases because of additional attenuation on the internal clock path. 6.10 switching characteristics typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit device (sampling) clock (clk+, clk ? ) t ad sampling (aperture) delay from clk rising edge (dual-channel mode) or rising and falling edge (single-channel mode) to sampling instant tad_coarse = 0x00, tad_fine = 0x00 and tad_inv = 0 360 ps t ad(max) maximum t ad adjust programmable delay, not including clock inversion (tad_inv = 0) coarse adjustment (tad_coarse = 0xff) 289 ps fine adjustment (tad_fine = 0xff) 4.9 t ad(step) t ad adjust programmable delay step size coarse adjustment (tad_coarse) 1.13 ps fine adjustment (tad_fine) 19 t aj aperture jitter, rms minimum t ad adjust coarse setting (tad_coarse = 0x00, tad_inv = 0) 50 fs maximum t ad adjust coarse setting (tad_coarse = 0xff) excluding tad_inv (tad_inv = 0) 70 (2) serial data outputs (da[7:0]+, da[7:0] ? , db[7:0]+, db[7:0] ? ) f serdes serialized output bit rate maximum output bit rate [9, 10, 11] 12.8 gbps minimum output bit rate [9, 10, 11] 1 3.2 gbps ui serialized output unit interval minimum output unit interval [9, 10, 11] 78.125 ps maximum output unit interval [9, 10, 11] 312.5 1000 ps t tlh low-to-high transition time (differential) 20% to 80%, prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04 37 ps t thl high-to-low transition time (differential) 20% to 80%, prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04 37 ps ddj data dependent jitter, peak-to-peak prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04, jmode = 2 7.8 ps rj random jitter, rms prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04, jmode = 2 1.1 ps advance information
21 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated switching characteristics (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit (3) t adc is an exact, unrounded, deterministic delay. the delay can be negative if the reference sample is sampled after the sysref high capture point, in which case the total latency is smaller than the delay given by t tx . tj total jitter, peak-to-peak, with gaussian portion defined with respect to a ber=1e-15 (q = 7.94) prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04, jmode = 0, 2 25 ps prbs-7 test pattern, 6.4 gbps, ser_pe = 0x04, jmode = 1, 3 21 prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 4, 5, 6, 7 28 prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 9 35 prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 10, 11 40 prbs-7 test pattern, 3.2 gbps, ser_pe = 0x04, jmode = 12 26 prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 13, 14 39 prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 15, 16 34 adc core latency t adc deterministic delay from the clk edge that samples the reference sample to the clk edge that samples sysref going high (3) jmode = 0 ? 8.5 t clk cycles jmode = 1 ? 20.5 jmode = 2 ? 9 jmode = 3 ? 21 jmode = 4 ? 4.5 jmode = 5 ? 24.5 jmode = 6 ? 5 jmode = 7 ? 25 jmode = 9 60 jmode = 10 140 jmode = 11 136 jmode = 12 120 jmode = 13 232 jmode = 14 232 jmode = 15 446 jmode = 16 430 jmode = 17 ? 48.5 jmode = 18 ? 49 advance information
22 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated switching characteristics (continued) typical values at t a = 25 c, va19 = 1.9 v, va11 = 1.1 v, vd11= 1.1 v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina in single-channel modes, f in = 248 mhz, a in = ? 1dbfs, f clk = maximum-rated clock frequency, filtered 1-v pp sine-wave clock, jmode = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the recommended operating conditions table parameter test conditions subgroup (1) min typ max unit (4) the values given for t tx include deterministic and non-deterministic delays. the delay varies over process, temperature, and voltage. jesd204b accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. proper receiver rbd values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (lmfc) cycle. (5) this parameter is specified by design and is not tested in production. jesd204b and serializer latency t tx delay from the clk rising edge that samples sysref high to the first bit of the multiframe on the jesd204b serial output lane corresponding to the reference sample of t adc (4) jmode = 0 72 (5) 84 (5) t clk cycles jmode = 1 119 (5) 132 (5) jmode = 2 72 (5) 84 (5) jmode = 3 119 (5) 132 (5) jmode = 4 67 (5) 80 (5) jmode = 5 106 (5) 119 (5) jmode = 6 67 (5) 80 (5) jmode = 7 106 (5) 119 (5) jmode = 9 106 (5) 119 (5) jmode = 10 67 (5) 80 (5) jmode = 11 106 (5) 119 (5) jmode = 12 213 (5) 225 (5) jmode = 13 67 (5) 80 (5) jmode = 14 106 (5) 119 (5) jmode = 15 67 (5) 80 (5) jmode = 16 106 (5) 119 (5) jmode = 17 195 (5) 208 (5) jmode = 18 195 (5) 208 (5) serial programming interface (sdo) t (ozd) delay from falling edge of 16th sclk cycle during read operation for sdo transition from tri-state to valid data 1 ns t (odz) delay from scs rising edge for sdo transition from valid data to tri-state 10 ns t (od) delay from falling edge of sclk during read operation to sdo valid 1 10 ns advance information
23 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) mil-std-883, method 5005 - group a table 1. quality conformance inspection (1) subgroup description temperature ( c) 1 static tests at 25 2 static tests at 125 3 static tests at ? 55 4 dynamic tests at 25 5 dynamic tests at 125 6 dynamic tests at ? 55 7 functional tests at 25 8a functional tests at 125 8b functional tests at ? 55 9 switching tests at 25 10 switching tests at 125 11 switching tests at ? 55 (1) only the serdes lane da0 is shown, but da0 is representative of all lanes. the number of output lanes used and bit-packing format is dependent on the programmed jmode value. figure 1. adc timing diagram advance information clk+ clk da0+/ (1) t ad t adc sysref+ sysref t su(sysref) t tx s 0 s 1 s 2 t clk s 0 s 1 s 2 t h(sysref) start of multi-frame
24 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (2) it is assumed that the internal lmfc is aligned with the rising edge of clk that captures the sysref high value. (3) only serdes lane da0 is shown, but da0 is representative of all lanes. all lanes output /r at approximately the same point in time. the number of lanes is dependent on the programmed jmode value. figure 2. syncse and tmstp timing diagram for nco synchronization figure 3. serial interface timing t h(scs) 1 st clock sclk 16 th clock 24 th clock scs t su(scs) t (odz) sdi t (ozd) d7 d0 d1 command field t (od) d7 d0 d1 sdo write command read command t su(sdi) t h(sdi) t (ph) t (pl) t (ph) + t (pl) = t (p) = 1 / | clk(sclk) hi-z hi-z t h(scs) t su(scs) t su(sdi) t h(sdi) clk+ clk da0+/ (2) sysref+ sysref /r syncse (sync_sel = 0) t h(syncse) t su(syncse) t tx start of ilas lmfc (1) (internal) one multi-frame one multi-frame tmstp+/ (sync_sel = 1) advance information
25 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the ADC12DJ3200QML-SP device is an rf-sampling, giga-sample, analog-to-digital converter (adc) that can directly sample input frequencies from dc to above 10 ghz. in dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 msps and up to 6400 msps in single-channel mode. programmable tradeoffs in channel count (dual-channel mode) and nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. full-power input bandwidth ( ? 3 db) of 7.0 ghz, with usable frequencies exceeding the ? 3-db point in both dual- and single- channel modes, allows direct rf sampling of l-band, s-band, c-band, and x-band for frequency agile systems. time interleaving is achieved internally through four active cores. in dual-channel mode, two cores are interleaved per channel to increase the sample rate to twice the core sample rate. in single-channel mode, all four cores are time interleaved to increase the sample rate to 4x the core sample rate. either input can be used in single-channel mode, however performance is optimized for ina . the user provides a clock at twice the adc core sample rate and the generation of the clocks for the interleaved cores is done internally for both single- channel mode and dual-channel mode. the ADC12DJ3200QML-SP also provides foreground and background calibration options to match the gain and offset between cores to minimize spurious artifacts from interleaving. this adc core is followed by a configurable digital down converter (ddc) block. the ddc block provides a range of decimation settings that allow the device to work in ultra-wideband, wideband, and more-narrow-band receive systems. additionally, a single adc channel (in dual-channel mode) can be muxed to separate ddc blocks for multi-band receive applications. the ADC12DJ3200QML-SP uses a high-speed jesd204b output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. the serial output lanes support up to 12.8 gbps and can be configured to trade-off bit rate and number of lanes. innovative synchronization features, including noiseless aperture delay (t ad ) adjustment and sysref windowing, simplify system design for synthetic aperture radar (sar) and phased-array mimo communications. optional digital down converters (ddcs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only). the ADC12DJ3200QML-SP has a single event latch-up tolerance to 120 mev-cm 2 /mg and a total ionizing dose to 300 krad (si) for radiation-sensitive applications. serial programming interface and programming registers are protected against radiation upsets while other key circuitry is monitored by alarms for quick detection of upsets. advance information
26 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.2 functional block diagram ddc bypass / single-channel mode sclk sdi sdo scs\ ncoa0 ncoa1 ncob0 ncob1 adc a jesd20 4b link a jesd20 4b link b aperture delay adjust clock distribution and synchronization clk+ clk sysref+ sysref syncse\ over- range da0+ da0 da7+ da7 db0+ db0 db7+ db7 status indicators ora0 ora1 orb0 orb1 calstat adc b tdiode+ tdiode caltrg pd spi registers and device control ina+ ina inb+ inb tmstp+ tmstp input mux input mux ddca mixer filter n nco bank a ddc bypass / single-channel mode ddc b mixer filter n nco bank b jmode jmode sysref windowing digbind advance information
27 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 analog inputs the analog inputs of the ADC12DJ3200QML-SP have internal buffers to enable high input bandwidth and to isolate sampling capacitor glitch noise from the input circuit. analog inputs must be driven differentially because operation with a single-ended signal results in degraded performance. both ac-coupling and dc-coupling of the analog inputs is supported. the analog inputs are designed for an input common-mode voltage (v cmi ) of 0 v, which is terminated internally through single-ended, 50- resistors to ground (gnd) on each input pin. dc- coupled input signals must have a common-mode voltage that meets the device input common-mode requirements specified as v cmi in the recommended operating conditions table. the 0-v input common-mode voltage simplifies the interface to split-supply, fully-differential amplifiers and to a variety of transformers and baluns. the ADC12DJ3200QML-SP includes internal analog input protection to protect the adc inputs during overranged input conditions; see the analog input protection section. figure 4 shows a simplified analog input model. figure 4. ADC12DJ3200QML-SP analog input internal termination and protection diagram there is minimal degradation in analog input bandwidth when using single-channel mode versus dual-channel mode. in single-channel mode, ina is strongly recommended to be used as the input to the adc because adc performance is optimized for ina . however, either analog input (ina+ and ina ? or inb+ and inb ? ) can be used. using inb results in degraded performance unless custom trim routines are used to optimize performance for inb in each device. the desired input can be chosen using single_input in the input mux control register . note ina is strongly recommended to be used as the input to the adc in single-channel mode for optimized performance. 7.3.1.1 analog input protection the analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of sourcing or sinking input currents during overrange conditions, see the voltage and current limits in the absolute maximum ratings table. the overrange protection is also defined for a peak rf input power in the absolute maximum ratings table, which is frequency independent. operation above the maximum conditions listed in the recommended operating conditions table results in an increase in failure-in-time (fit) rate, so the system must correct the overdrive condition as quickly as possible. figure 4 shows the analog input protection diodes. adc 50 50 ina+, inb+ ina , inb agnd analog input protection diodes input buffer advance information
28 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.1.2 full-scale voltage (v fs ) adjustment input full-scale voltage (v fs ) adjustment is available, in fine increments, for each analog input through the fs_range_a register setting (see the ina full-scale range adjust register ) and fs_range_b register setting (see the inb full-scale range adjust register ) for ina and inb , respectively. the available adjustment range is specified in the electrical characteristics: dc specifications table. larger full-scale voltages improve snr and noise floor (in dbfs/hz) performance, but can degrade harmonic distortion. the full-scale voltage adjustment is useful for matching the full-scale range of multiple adcs when developing a multi-converter system or for external interleaving of multiple ADC12DJ3200QML-SPs to achieve higher sampling rates. 7.3.1.3 analog input offset adjust the input offset voltage for each input can be adjusted through the oadj_x_iny registers (registers 0x08a and 0x095), where x represents the adc core (a, b, or c) and y represents the analog input (ina or inb ). the adjustment range is approximately 28 mv to ? 28 mv differential. see the calibration modes and trimming section for more information. 7.3.2 adc core the ADC12DJ3200QML-SP consists of a total of six adc cores. the cores are interleaved for higher sampling rates and swapped on-the-fly for calibration as required by the operating mode. this section highlights the theory and key features of the adc cores. 7.3.2.1 adc theory of operation the differential voltages at the analog inputs are captured by the rising edge of clk in dual-channel mode or by the rising and falling edges of clk in single-channel mode. after capturing the input signal, the adc converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. if the voltage on ina ? or inb ? is higher than the voltage on ina+ or inb+, respectively, then the digital output is a negative 2's complement value. if the voltage on ina+ or inb+ is higher than the voltage on ina ? or inb ? , respectively, then the digital output is a positive 2's complement value. equation 1 can calculate the differential voltage at the input pins from the digital output. where ? code is the signed decimation output code (for example, ? 2048 to +2047) ? n is the adc resolution ? and v fs is the full-scale input voltage of the adc as specified in the recommended operating conditions table, including any adjustment performed by programming fs_range_a or fs_range_b (1) 7.3.2.2 adc core calibration adc core calibration is required to optimize the analog performance of the adc cores. calibration must be repeated when operating conditions change significantly, namely temperature, in order to maintain optimal performance. the ADC12DJ3200QML-SP has a built-in calibration routine that can be run as a foreground operation or a background operation. foreground operation requires adc downtime, where the adc is no longer sampling the input signal, to complete the process. background calibration can be used to overcome this limitation and allow constant operation of the adc. see the calibration modes and trimming section for detailed information on each mode. in fs n code v v 2 advance information
29 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.2.3 adc overrange detection to make sure that system gain management has the quickest possible response time, a low-latency configurable overrange function is included. the overrange function works by monitoring the converted 12-bit samples at the adc to quickly detect if the adc is near saturation or already in an overrange condition. the absolute value of the upper 8 bits of the adc data are checked against two programmable thresholds, ovr_t0 and ovr_t1. these thresholds apply to both channel a and channel b in dual-channel mode. table 2 lists how an adc sample is converted to an absolute value for a comparison of the thresholds. table 2. conversion of adc sample for overrange comparison adc sample (offset binary) adc sample (2's complement) absolute value upper 8 bits used for comparison 1111 1111 1111 (4095) 0111 1111 1111 (+2047) 111 1111 1111 (2047) 1111 1111 (255) 1111 1111 0000 (4080) 0111 1111 0000 (+2032) 111 1111 0000 (2032) 1111 1110 (254) 1000 0000 0000 (2048) 0000 0000 0000 (0) 000 0000 0000 (0) 0000 0000 (0) 0000 0001 0000 (16) 1000 0001 0000 ( ? 2032) 111 1111 0000 (2032) 1111 1110 (254) 0000 0000 0000 (0) 1000 0000 0000 ( ? 2048) 111 1111 1111 (2047) 1111 1111 (255) if the upper 8 bits of the absolute value equal or exceed the ovr_t0 or ovr_t1 thresholds during the monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is 0. in dual-channel mode, the overrange status can be monitored on the ora0 and ora1 pins for channel a and the orb0 and orb1 pins for channel b, where orx0 corresponds to the ovr_t0 threshold and orx1 corresponds to the ovr_t1 threshold. in single-channel mode, the overrange status for the ovr_t0 threshold is determined by monitoring both the ora0 and orb0 outputs and the ovr_t1 threshold is determined by monitoring both ora1 and orb1 outputs. in single-channel mode, the two outputs for each threshold must be or'd together to determine whether an overrange condition occurred. ovr_n can be used to set the output pulse duration from the last overrange event. table 3 lists the overrange pulse lengths for the various ovr_n settings (see the overrange configuration register ). in decimation modes (only in the jmodes where cs = 1 in table 19 ), the overrange status is also embedded into the output data samples. for complex decimation modes, the ovr_t0 threshold status is embedded as the lsb along with the upper 15 bits of every complex i sample and the ovr_t1 threshold status is embedded as the lsb along with the upper 15 bits of every complex q sample. for real decimation modes, the ovr_t0 threshold status is embedded as the lsb of every even- numbered sample and the ovr_t1 threshold status is embedded as the lsb of every odd-numbered sample. table 4 lists the outputs, related data samples, threshold settings, and the monitoring period equation. the embedded overrange bit goes high if the associated channel exceeds the associated overrange threshold within the monitoring period set by ovr_n. use table 4 to calculate the monitoring period. table 3. overrange monitoring period for the ora0, ora1, orb0, and orb1 outputs ovr_n overrange pulse length since last overrange event (devclk cycles) 0 8 1 16 2 32 3 64 4 128 5 256 6 512 7 1024 advance information
30 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) ovr_n is the monitoring period register setting. table 4. threshold and monitoring period for embedded overrange indicators in dual-channel decimation modes overrange indicator associated threshold decimation type overrange status embedded in monitoring period (adc samples) ora0 ovr_t0 real decimation (jmode 9) channel a even- numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel a in-phase (i) samples 2 ovr_n (1) ora1 ovr_t1 real decimation (jmode 9) channel a odd- numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel a quadrature (q) samples 2 ovr_n (1) orb0 ovr_t0 real decimation (jmode 9) channel b even- numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel b in-phase (i) samples 2 ovr_n (1) orb1 ovr_t1 real decimation (jmode 9) channel b odd- numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel b quadrature (q) samples 2 ovr_n (1) typically, the ovr_t0 threshold can be set near the full-scale value (228 for example). when the threshold is triggered, a typical system can turn down the system gain to avoid clipping. the ovr_t1 threshold can be set much lower. for example, the ovr_t1 threshold can be set to 64 (peak input voltage of ? 12 dbfs). if the input signal is strong, the ovr_t1 threshold is tripped occasionally. if the input is quite weak, the threshold is never tripped. the downstream logic device monitors the ovr_t1 bit. if ovr_t1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above ? 12 dbfs). 7.3.2.4 code error rate (cer) adc cores can generate bit errors within a sample, often called code errors (cer) or referred to as sparkle codes , resulting from metastability caused by non-ideal comparator limitations. the ADC12DJ3200QML-SP uses a unique adc architecture that inherently allows significant code error rate improvements from traditional pipelined flash or successive approximation register (sar) adcs. the code error rate of the ADC12DJ3200QML-SP is multiple orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing significant signal reliability improvements. 7.3.3 timestamp the tmstp+ and tmstp ? differential input can be used as a time-stamp input to mark a specific sample based on the timing of an external trigger event relative to the sampled signal. timestamp_en (see the lsb control bit output register ) must be set in order to use the timestamp feature and output the timestamp data. when enabled, the lsb of the 12-bit adc digital output reports the status of the tmstp input. in effect, the 12-bit output sample consists of the upper 11-bits of the 12-bit converter and the lsb of the 12-bit output sample is the output of a parallel 1-bit converter (tmstp ) with the same latency as the adc core. in the 8-bit operating modes, the lsb of the 8-bit output sample is used to output the timestamp status. the trigger must be applied to the differential tmstp+ and tmstp ? inputs. the trigger can be asynchronous to the adc sampling clock and is sampled at approximately the same time as the analog input. timestamp cannot be used when a jmode with decimation is selected and instead sysref must be used to achieve synchronization through the jesd204b subclass-1 method for achieving deterministic latency. advance information
31 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.4 clocking the clocking subsystem of the ADC12DJ3200QML-SP has two input signals, device clock (clk+, clk ? ) and sysref (sysref+, sysref ? ). within the clocking subsystem there is a noiseless aperture delay adjustment (t ad adjust), a clock duty cycle corrector, and a sysref capture block. figure 5 shows the clocking subsystem. figure 5. ADC12DJ3200QML-SP clocking subsystem the device clock is used as the sampling clock for the adc core as well as the clocking for the digital processing and serializer outputs. use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (snr) within the adc. in dual-channel mode, the analog input signal for each input is sampled on the rising edge of the device clock. in single-channel mode, both the rising and falling edges of the device clock are used to capture the analog signal to reduce the maximum clock rate required by the adc. a noiseless aperture delay adjustment (t ad adjust) allows the user to shift the sampling instance of the adc in fine steps in order to synchronize multiple ADC12DJ3200QML-SPs or to fine-tune system latency. duty cycle correction is implemented in the ADC12DJ3200QML-SP to ease the requirements on the external device clock while maintaining high performance. table 5 summarizes the device clock interface in dual-channel mode and single-channel mode. table 5. device clock vs mode of operation mode of operation sampling rate vs f clk sampling instant dual-channel mode 1 f clk rising edge single-channel mode 2 f clk rising and falling edge sysref is a system timing reference used for jesd204b subclass-1 implementations of deterministic latency. sysref is used to achieve deterministic latency and for multi-device synchronization. sysref must be captured by the correct device clock edge in order to achieve repeatable latency and synchronization. the ADC12DJ3200QML-SP includes sysref windowing and automatic sysref calibration to ease the requirements on the external clocking circuits and to simplify the synchronization process. sysref can be implemented as a single pulse or as a periodic clock. in periodic implementations, sysref must be equal to, or an integer division of, the local multiframe clock frequency. equation 2 is used to calculate valid sysref frequencies. where ? r and f are set by the jmode setting (see table 19 ) ? f clk is the device clock frequency (clk ) ? k is the programmed multiframe length (see table 19 for valid k settings) ? and n is any positive integer (2) clk sysref r f f 10 f k n u u u u advance information sysref capture t ad adjust clock distribution and synchronization (adc cores, digital, jesd204b, etc.) clk+ clk- sysref+ sysref- sysref windowing automatic sysref calibration sysref_pos sysref_sel tad_inv tad_coarse tad_ fine src_en duty cycle correction
32 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.4.1 noiseless aperture delay adjustment (t ad adjust) the ADC12DJ3200QML-SP contains a delay adjustment on the device clock (sampling clock) input path, called t ad adjust, that can be used to shift the sampling instance within the device in order to align sampling instances among multiple devices or for external interleaving of multiple ADC12DJ3200QML-SPs. further, t ad adjust can be used for automatic sysref calibration to simplify synchronization; see the automatic sysref calibration section. aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a slight degradation in aperture jitter (t aj ) is possible at large values of tad_coarse because of internal clock path attenuation. the degradation in aperture jitter results in minor snr degradations at high input frequencies (see t aj in the switching characteristics table). this feature is programmed using tad_inv, tad_coarse, and tad_fine in the devclk timing adjust ramp control register . setting tad_inv inverts the input clock resulting in a delay equal to half the clock period. table 6 summarizes the step sizes and ranges of the tad_coarse and tad_fine variable analog delays. all three delay options are independent and can be used in conjunction. all clocks within the device are shifted by the programmed t ad adjust amount, which results in a shift of the timing of the jesd204b serialized outputs and affects the capture of sysref. table 6. t ad adjust adjustment ranges adjustment parameter adjustment step delay settings maximum delay tad_inv 1 / (f clk 2) 1 1 / (f clk 2) tad_coarse see t tad(step) in the switching characteristics table 256 see t tad(max) in the switching characteristics table tad_fine see t tad(step) in the switching characteristics table 256 see t tad(max) in the switching characteristics table in order to maintain timing alignment between converters, stable and matched power-supply voltages and device temperatures must be provided. aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to the jesd204b data link. use tad_ramp to reduce the probability of the jesd204b link losing synchronization; see the aperture delay ramp control (tad_ramp) section. 7.3.4.2 aperture delay ramp control (tad_ramp) the ADC12DJ3200QML-SP contains a function to gradually adjust the t ad adjust setting towards the newly written tad_coarse value. this functionality allows the t ad adjust setting to be adjusted with minimal internal clock circuitry glitches. the tad_ramp_rate parameter allows either a slower (one tad_coarse lsb per 256 t clk cycles) or faster ramp (four tad_coarse lsbs per 256 t clk cycles) to be selected. the tad_ramp_en parameter enables the ramp feature and any subsequent writes to tad_coarse initiate a new cramp. 7.3.4.3 sysref capture for multi-device synchronization and deterministic latency the clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic latency. the ADC12DJ3200QML-SP uses the jesd204b subclass-1 method to achieve deterministic latency and synchronization. subclass 1 requires that the sysref signal be captured by a deterministic device clock (clk ) edge at each system power-on and at each device in the system. this requirement imposes setup and hold constraints on sysref relative to clk , which can be difficult to meet at giga-sample clock rates over all system operating conditions. the ADC12DJ3200QML-SP includes a number of features to simplify this synchronization process and to relax system timing constraints: ? the ADC12DJ3200QML-SP uses dual-edge sampling (des) in single-channel mode to reduce the clk input frequency by half and double the timing window for sysref (see table 5 ) ? a sysref position detector (relative to clk ) and selectable sysref sampling position aid the user in meeting setup and hold times over all conditions; see the sysref position detector and sampling position selection (sysref windowing) section ? easy-to-use automatic sysref calibration uses the aperture timing adjust block (t ad adjust) to shift the adc sampling instance based on the phase of sysref (rather than adjusting sysref based on the phase of the adc sampling instance); see the automatic sysref calibration section advance information
33 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) red coloration indicates the bits that are selected, as given in the last column of this table. 7.3.4.3.1 sysref position detector and sampling position selection (sysref windowing) the sysref windowing block is used to first detect the position of sysref relative to the clk rising edge and then to select a desired sysref sampling instance, which is a delay version of clk , to maximize setup and hold timing margins. in many cases a single sysref sampling position (sysref_sel) is sufficient to meet timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). however, this feature can also be used by the system to expand the timing window by tracking the movement of sysref as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system. this section describes proper usage of the sysref windowing block. first, apply the device clock and sysref to the device. the location of sysref relative to the device clock cycle is determined and stored in the sysref_pos bits of the sysref capture position register . each bit of sysref_pos represents a potential sysref sampling position. if a bit in sysref_pos is set to 1, then the corresponding sysref sampling position has a potential setup or hold violation. upon determining the valid sysref sampling positions (the positions of sysref_pos that are set to 0) the desired sampling position can be chosen by setting sysref_sel in the clock control register 0 to the value corresponding to that sysref_pos position. in general, the middle sampling position between two setup and hold instances is chosen. ideally, sysref_pos and sysref_sel are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide maximum margin for operating condition variations. this process can be performed at final test and the optimal sysref_sel setting can be stored for use at every system power up. further, sysref_pos can be used to characterize the skew between clk and sysref over operating conditions for a system by sweeping the system temperature and supply voltages. for systems that have large variations in clk to sysref skew, this characterization can be used to track the optimal sysref sampling position as system operating conditions change. in general, a single value can be found that meets timing over all conditions for well-matched systems, such as those where clk and sysref come from a single clocking device. note sysref_sel must be set to 0 when using automatic sysref calibration; see the automatic sysref calibration section. the step size between each sysref_pos sampling position can be adjusted using sysref_zoom. when sysref_zoom is set to 0, the delay steps are coarser. when sysref_zoom is set to 1, the delay steps are finer. see the switching characteristics table for delay step sizes when sysref_zoom is enabled and disabled. in general, sysref_zoom is recommended to always be used (sysref_zoom = 1) unless a transition region (defined by 1's in sysref_pos) is not observed, which can be the case for low clock rates. bits 0 and 23 of sysref_pos are always be set to 1 because there is insufficient information to determine if these settings are close to a timing violation, although the actual valid window can extend beyond these sampling positions. the value programmed into sysref_sel is the decimal number representing the desired bit location in sysref_pos. table 7 lists some example sysref_pos readings and the optimal sysref_sel settings. although 24 sampling positions are provided by the sysref_pos status register, sysref_sel only allows selection of the first 16 sampling positions, corresponding to sysref_pos bits 0 to 15. the additional sysref_pos status bits are intended only to provide additional knowledge of the sysref valid window. in general, lower values of sysref_sel are selected because of delay variation over supply voltage, however in the fourth example a value of 15 provides additional margin and can be selected instead. table 7. examples of sysref_pos readings and sysref_sel selections sysref_pos[23:0] optimal sysref_sel setting 0x02e[7:0] (largest delay) 0x02d[7:0] (1) 0x02c[7:0] (1) (smallest delay) b10000000 b011000 00 b00011001 8 or 9 b10011000 b000 0 0000 b00110001 12 b10000000 b01100000 b 00 000001 6 or 7 b10000000 b 0 0000011 b000 0 0001 4 or 15 b10001100 b01100011 b0 0 011001 6 advance information
34 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.4.3.2 automatic sysref calibration the ADC12DJ3200QML-SP has an automatic sysref calibration feature to alleviate the often challenging setup and hold times associated with capturing sysref for giga-sample data converters. automatic sysref calibration uses the t ad adjust feature to shift the device clock to maximize the sysref setup and hold times or to align the sampling instance based on the sysref rising edge. the ADC12DJ3200QML-SP must have a proper device clock applied and be programmed for normal operation before starting the automatic sysref calibration. when ready to initiate automatic sysref calibration, a continuous sysref signal must be applied. sysref must be a continuous (periodic) signal when using the automatic sysref calibration. start the calibration process by setting src_en high in the sysref calibration enable register after configuring the automatic sysref calibration using the src_cfg register. upon setting src_en high, the ADC12DJ3200QML-SP searches for the optimal t ad adjust setting until the device clock falling edge is internally aligned to the sysref rising edge. tad_done in the sysref calibration status register can be monitored to make sure that the sysref calibration has finished. by aligning the device clock falling edge with the sysref rising edge, automatic sysref calibration maximizes the internal sysref setup and hold times relative to the device clock and also sets the sampling instant based on the sysref rising edge. after the automatic sysref calibration finishes, the rest of the startup procedure can be performed to finish bringing up the system. for multi-device synchronization, the sysref rising edge timing must be matched at all devices and therefore trace lengths must be matched from a common sysref source to each ADC12DJ3200QML-SP. any skew between the sysref rising edge at each device results in additional error in the sampling instance between devices, however repeatable deterministic latency from system startup to startup through each device must still be achieved. no other design requirements are needed in order to achieve multi-device synchronization as long as a proper elastic buffer release point is chosen in the jesd2048 receiver. figure 6 shows a timing diagram of the sysref calibration procedure. the optimized setup and hold times are shown as t su(opt) and t h(opt) , respectively. device clock and sysref are referred to as internal in this diagram because the phase of the internal signals are aligned within the device and not to the external (applied) phase of the device clock or sysref. figure 6. sysref calibration timing diagram advance information sampled input signal internal unadjusted device clock internal sysref src_en (spi register bit) t h(opt) t su(opt) internal calibrated device clock before calibration, device clock falling edge does not align with sysref rising edge t tad(src) calibration enabled after calibration, device clock falling edge aligns with sysref rising edge t cal(src) tad_done (spi register bit) calibration finished
35 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated when finished, the t ad adjust setting found by the automatic sysref calibration can be read from src_tad in the sysref calibration status register . after calibration, the system continues to use the calibrated t ad adjust setting for operation until the system is powered down. however, if desired, the user can then disable the sysref calibration and fine-tune the t ad adjust setting according to the systems needs. alternatively, the use of the automatic sysref calibration can be done at product test (or periodic recalibration) of the optimal t ad adjust setting for each system. this value can be stored and written to the tad register (tad_inv, tad_coarse, and tad_fine) upon system startup. do not run the sysref calibration when the adc calibration (foreground or background) is running. if background calibration is the desired use case, disable the background calibration when the sysref calibration is used, then reenable the background calibration after tad_done goes high. sysref_sel in the clock control register 0 must be set to 0 when using sysref calibration. sysref calibration searches the tad_coarse delays using both noninverted (tad_inv = 0) and inverted clock polarity (tad_inv = 1) to minimize the required tad_coarse setting in order to minimize loss on the clock path to reduce aperture jitter (t aj ). 7.3.5 digital down converters (dual-channel mode only) after converting the analog voltage to a digital value, the digitized sample can either be sent directly to the jesd204b interface block (ddc bypass) or sent to the digital down conversion (ddc) block for frequency conversion and decimation (in dual-channel mode only). frequency conversion and decimation allow a specific frequency band to be selected and output in the digital data stream while reducing the effective data rate and interface speed or width. the ddc is designed such that the digital processing does not degrade the noise spectral density (nsd) performance of the adc. table 116 illustrates the digital down converter for channel a of the ADC12DJ3200QML-SP. channel b has the same structure with the input data selected by dig_bind_b and the nco selection mux controlled by pins ncob[1:0] or through cselb[1:0]. figure 7. channel a digital down conversion block (dual-channel mode only) advance information nco bank a complex mixer n mux ncoa[1:0] or csela[1:0] 2 decimate-by-n (based on jmode) spectral inversion 2 mux high pass low pass mux mux real 12-bit at fs complex 15-bit at fs/n 2 real 15-bit at fs/2 mux dig_bind_a d2_high_pass invert_spectrum mux jmode (ddc bypass) jmode adc channel a adc channel b jesd204b
36 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.5.1 numerically-controlled oscillator and complex mixer the ddc contains a complex numerically-controlled oscillator (nco) and a complex mixer. equation 3 shows the complex exponential sequence generated by the oscillator. x[n] = e j n (3) the frequency ( ) is specified by a 32-bit register setting. the complex exponential sequence is multiplied by the real input from the adc to mix the desired carrier to a frequency equal to f in + f nco , where f in is the analog input frequency after aliasing (in undersampling systems) and f nco is the programmed nco frequency. 7.3.5.1.1 nco fast frequency hopping (ffh) fast frequency hopping (ffh) is made possible by each ddc having four independent ncos that can be controlled by the ncoa0 and ncoa1 pins for ddc a and the ncob0 and ncob1 pins for ddc b. each nco has independent frequency settings (see the basic nco frequency setting mode section) and initial phase settings (see the nco phase offset setting section) that can be set independently. further, all ncos have independent phase accumulators that continue to run when the specific nco is not selected, allowing the ncos to maintain their phase between selection so that downstream processing does not need to perform carrier recovery after each hop, for instance. nco hopping occurs when the nco gpio pins change state. the pins are controlled asynchronously and therefore synchronous switching is not possible. associated latencies are demonstrated in figure 8 , where t tx and t adc are provided in the switching characteristics table. all latencies in table 8 are approximations only. figure 8. nco fast frequency hopping latency diagram table 8. nco fast frequency hopping latency definitions latency parameter value or calculation units t gpio-mixer ~36 to ~40 t clk cycles t adc-mixer ~36 t clk cycles t mixer-tx (t tx + t adc ) ? t adc-mixer t clk cycles ddc block nco bank a complex mixer n mux ncox[1:0] decimate-by-n (based on jmode) adc jesd204b t gpio-mixer t mixer-tx dx0 dx1 dx2 dx7 inx+ inx t adc-mixer advance information
37 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.5.1.2 nco selection within each channel ddc, four different frequency and phase settings are available for use. each of the four settings use a different phase accumulator within the nco. because all four phase accumulators are independent and continuously running, rapid switching between different nco frequencies is possible allowing for phase coherent frequency hopping. the specific frequency-phase pair used for each channel is selected through the ncoa[1:0] or ncob[1:0] input pins when cmode is set to 1. alternatively, the selected nco can be chosen through spi by csela for ddc a and cselb for ddc b by setting cmode to 0 (default). the logic table for nco selection is provided in table 9 for both the gpio and spi selection options. table 9. logic table for nco selection using gpio or spi nco selection cmode ncox1 ncox0 cselx[1] cselx[0] nco 0 using gpio 1 0 0 x x nco 1 using gpio 1 0 1 x x nco 2 using gpio 1 1 0 x x nco 3 using gpio 1 1 1 x x nco 0 using spi 0 x x 0 0 nco 1 using spi 0 x x 0 1 nco 2 using spi 0 x x 1 0 nco 3 using spi 0 x x 1 1 the frequency for each phase accumulator is programmed independently through the freqax, freqbx (x = 0 to 3) and, optionally, nco_rdiv register settings. the phase offset for each accumulator is programmed independently through the phaseax and phasebx (x = 0 to 3) register settings. 7.3.5.1.3 basic nco frequency setting mode in basic nco frequency-setting mode (nco_rdiv = 0x0000), the nco frequency setting is set by the 32-bit register value, freqax and freqbx (x = 0 to 3). the nco frequency for ddc a can be calculated using equation 4 , where freqax can be replaced by freqbx to calculate the nco frequency for ddc b. ? (nco) = freqax 2 ? 32 ? (devclk) (x = 0 ? 3) (4) note changing the freqax and freqbx register settings during operation results in a non- deterministic nco phase. if deterministic phase is required, the ncos must be resynchronized; see the nco phase synchronization section. 7.3.5.1.4 rational nco frequency setting mode in basic nco frequency mode, the frequency step size is very small and many frequencies can be synthesized, but sometimes an application requires very specific frequencies that fall between two frequency steps. for example with ? s equal to 2457.6 mhz and a desired ? (nco) equal to 5.02 mhz, the value for freqax is 8773085.867. truncating the fractional portion results in an ? (nco) equal to 5.0199995 mhz, which is not the desired frequency. to produce the desired frequency, the nco_rdiv parameter is used to force the phase accumulator to arrive at specific frequencies without error. first, select a frequency step size ( ? (step) ) that is appropriate for the nco frequency steps required. the typical value of ? (step) is 10 khz. next, use equation 5 to program the nco_rdiv value. (5) the result of equation 5 must be an integer value. if the value is not an integer, adjust either of the parameters until the result is an integer value. advance information ( ) devclk step / nco _ rdiv 64 | | =
38 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated for example, select a value of 1920 for nco_rdiv. note nco_rdiv values larger than 8192 can degrade the nco sfdr performance and are not recommended. now use equation 6 to calculate the freqax register value. (6) alternatively, the following equations can be used: (7) (8) table 10 lists common values for nco_rdiv in 10-khz frequency steps. table 10. common nco_rdiv values (for 10-khz frequency steps) f clk (mhz) nco_rdiv 3200 5000 3072 4800 2949.12 4608 2457.6 3840 1966.08 3072 1600 2500 1474.56 2304 1228.8 1920 7.3.5.1.5 nco phase offset setting the nco phase-offset setting for each nco is set by the 16-bit register value phaseax and phasebx (where x = 0 to 3). the value is left-justified into a 32-bit field and then added to the phase accumulator. use equation 9 to calculate the phase offset in radians. (rad) = phasea/bx 2 ? 16 2 (x=0 to 3) (9) 7.3.5.1.6 nco phase synchronization the ncos must be synchronized after setting or changing the value of freqax or freqbx. nco synchronization is performed when the jesd204b link is initialized or by sysref, based on the settings of nco_sync_ila and nco_sync_next. the procedures are as follows for the jesd204b initialization procedure and the sysref procedure for both dc-coupled and ac-coupled sysref signals. nco synchronization using the jesd204b sync signal ( syncse or tmstp ): 1. the device must be programmed for normal operation 2. set nco_sync_ila to 1 3. set jesd_en to 0 4. program freqax, freqbx, phaseax, and phasebx to the desired settings 5. in the jesd204b receiver (logic device), deassert the sync signal by setting sync high 6. set jesd_en to 1 7. assert the sync signal by setting sync low in the jesd204b receiver to start the code group synchronization (cgs) process 8. after achieving cgs, deassert the sync signal by setting sync high at the same time for all adcs to be synchronized and verify that the sync setup and hold times are met (as specified in the timing requirements table) (nco) (step) | n | ( ) 26 freqax round 2 n / nco_rdiv = advance information ( ) 32 nco devclk freqax / round 2 = | |
39 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated nco synchronization using sysref (dc-coupled): 1. the device must be programmed for normal operation 2. set jesd_en to 1 to start the jesd204b link (the sync signal can respond as normal during the cgs process) 3. program freqax, freqbx, phaseax, and phasebx to the desired settings 4. verify that sysref is disabled (held low) 5. arm nco synchronization by setting nco_sync_next to 1 6. issue a single sysref pulse to all adcs to synchronize ncos within all devices nco synchronization using sysref (ac-coupled): 1. the device must be programmed for normal operation 2. set jesd_en to 1 to start the jesd204b link (the sync signal can respond as normal during the cgs process) 3. program freqax, freqbx, phaseax, and phasebx to the desired settings 4. run sysref continuously 5. arm nco synchronization by setting nco_sync_next to 1 at the same time at all adcs by timing the rising edge of sclk for the last data bit (lsb) at the end of the spi write so that the sclk rising edge occurs after a sysref rising edge and early enough before the next sysref rising edge so that the trigger is armed before the next sysref rising edge (a long sysref period is recommended) 6. ncos in all adcs are synchronized by the next sysref rising edge 7.3.5.2 decimation filters the decimation filters are arranged to provide a programmable overall decimation of 2, 4, 8, or 16. all filter outputs have a resolution of 15 bits. the decimate-by-2 filter has a real output and the decimate-by-4, decimate- by-8, and decimate-by-16 filters have complex outputs. table 11 lists the effective output sample rates, available signal bandwidths, output formats, and stop-band attenuation for each decimation mode. the available bandwidths of the complex output modes are twice that of equivalent real decimation modes because of the nature of the i/q data and complex signaling. this higher bandwidth results in the decimate-by-2 real and decimate-by-4 complex modes having approximately the same useful output bandwidth. table 11. output sample rates and signal bandwidths decimation setting ? (devclk) output format output rate (msps) max alias protected signal bandwidth (mhz) stop-band attenuation pass-band ripple no decimation ? (devclk) ? (devclk) / 2 ? < 0.001 db real signal, 12-bit data decimate-by-2 ? (devclk) / 2 0.4 ? (devclk) / 2 > 89 db < 0.001 db real signal, 15-bit data decimate-by-4 (d4_ap87 = 0) ? (devclk) / 4 0.8 ? (devclk) / 4 > 90 db < 0.001 db complex signal, 15- bit data decimate-by-4 (d4_ap87 = 1) ? (devclk) / 4 0.875 ? (devclk) / 4 > 66 db < 0.005 db complex signal, 15- bit data decimate-by-8 ? (devclk) / 8 0.8 ? (devclk) / 8 > 90 db < 0.001 db complex signal, 15- bit data decimate-by-16 ? (devclk) / 16 0.8 ? (devclk) / 16 > 90 db < 0.001 db complex signal, 15- bit data figure 9 to figure 20 provide the composite decimation filter responses. the pass-band section (black trace) shows the alias-protected region of the response. the transition band (red trace) shows the transition region of the response, or the regions that alias into the transition region, which is not alias protected and therefore desired signals must not be within this band. the aliasing band (blue trace) shows the attenuation applied to the bands that alias back into the pass band after decimation and are sufficiently low to prevent undesired signals from showing up in the pass band. use analog input filtering for additional attenuation of the aliasing band or to prevent harmonics, interleaving spurs, or other undesired spurious signals from folding into the desired signal band before the decimation filter. advance information
40 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated figure 9. decimate-by-2 composite response (d2_high_pass = 0) figure 10. decimate-by-2 composite zoomed pass-band response (d2_high_pass = 0) figure 11. decimate-by-2 composite response (d2_high_pass = 1) figure 12. decimate-by-2 composite zoomed pass-band response (d2_high_pass = 1) figure 13. decimate-by-4 composite response (d4_ap87 = 0) figure 14. decimate-by-4 composite zoomed pass-band response (d4_ap87 = 0) normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h2co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0.25 0.3 0.35 0.4 0.45 0.5 -0.001 -0.0005 0 0.0005 0.001 h2co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h2co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.05 0.1 0.15 0.2 0.25 -0.001 -0.0005 0 0.0005 0.001 h2co passband transition band advance information normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h4co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 -0.001 -0.0005 0 0.0005 0.001 h4co passband transition band
41 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated figure 15. decimate-by-4 composite response (d4_ap87 = 1) figure 16. decimate-by-4 composite zoomed pass-band response (d4_ap87 = 1) figure 17. decimate-by-8 composite response figure 18. decimate-by-8 composite zoomed pass-band response figure 19. decimate-by-16 composite response figure 20. decimate-by-16 composite zoomed pass-band response normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h16c passband transition band aliasing band advance information normalized frequency (fs) attenuation (db) 0 0.005 0.01 0.015 0.02 0.025 0.03 -0.001 -0.0005 0 0.0005 0.001 h16c passband transition band normalized frequency (fs) attenuation (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 -0.01 -0.005 0 0.005 0.01 h4_9 passband transition band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h4_9 passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.01 0.02 0.03 0.04 0.05 0.06 -0.001 -0.0005 0 0.0005 0.001 h8co passband transition band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h8co passband transition band aliasing band
42 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated for maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each decimation setting to achieve the composite responses illustrated in figure 9 to figure 20 . table 12 describes the combination of filter blocks used for each decimation setting and table 13 lists the coefficient details and decimation factor of each filter block. the coefficients are symmetric with the center tap indicated by bold text. table 12. decimation mode filter usage decimation setting filter blocks used 2 cs80 4 (d4_ap87 = 0) cs45, cs80 4 (d4_ap87 = 1) cs45, cs87 8 cs20, cs40, cs80 16 cs10, cs20, cs40, cs80 table 13. filter coefficient details filter coefficient set (decimation factor of filter) cs10 (2) cs20 (2) cs40 (2) cs45 (2) cs80 (2) cs87 (2) ? 65 ? 65 109 109 ? 327 ? 327 56 56 ? 37 ? 37 ? 15 ? 15 0 0 0 0 0 0 0 0 0 0 0 0 577 577 ? 837 ? 837 2231 2231 ? 401 ? 401 118 118 23 23 1024 0 0 0 0 0 0 0 0 0 0 4824 4824 ? 8881 ? 8881 1596 1596 ? 291 ? 291 ? 40 ? 40 8192 0 0 0 0 0 0 0 0 39742 39742 ? 4979 ? 4979 612 612 64 64 65536 0 0 0 0 0 0 20113 20113 ? 1159 ? 1159 ? 97 ? 97 32768 0 0 0 0 2031 2031 142 142 0 0 0 0 ? 3356 ? 3356 ? 201 ? 201 0 0 0 0 5308 5308 279 279 0 0 0 0 ? 8140 ? 8140 ? 380 ? 380 0 0 0 0 12284 12284 513 513 0 0 0 0 ? 18628 ? 18628 ? 690 ? 690 0 0 0 0 29455 29455 939 939 0 0 0 0 ? 53191 ? 53191 ? 1313 ? 1313 0 0 0 0 166059 166059 1956 1956 262144 0 0 ? 3398 ? 3398 0 0 10404 10404 16384 advance information
43 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.5.3 output data format the ddc output data varies depending on the selected jmode. real decimate-by-2 mode (jmode 9) consists of 15-bit real output data. complex decimation modes (jmode 10 to 16), except for jmode 12, consist of 15-bit complex data plus the two overrange threshold-detection control bits. jmode 12 output data consists of 12-bit complex data, but does not include the two overrange threshold-detection control bits that must instead be monitored using the ora0, ora1 and orb0, orb1 output pins. figure 36 lists the data format for jmode 9 and table 15 lists the data format for all jmodes except jmode 12. table 14. real decimation (jmode 9) output sample format ddc channel odd, even sample 16-bit output word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a even ddc a even-numbered sample, 15-bit output data ovr_t0 a odd ddc a odd-numbered sample, 15-bit output data ovr_t1 b even ddc b even-numbered sample, 15-bit output data ovr_t0 b odd ddc b odd-numbered sample, 15-bit output data ovr_t1 table 15. complex decimation output sample format (except jmode 12) i/q sample 16-bit output word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i ddc in-phase (i) 15-bit output data ovr_t0 q ddc quadrature (q) 15-bit output data ovr_t1 7.3.5.4 decimation settings 7.3.5.4.1 decimation factor the decimation setting is adjustable over the following settings and is set by the jmode parameter. see table 19 for the available jmode values and the corresponding decimation settings. ? ddc bypass: no decimation, real output ? decimate-by-2: real output (jmode 9) ? decimate-by-4: complex output (jmode 10 to 12) ? decimate-by-8: complex output (jmode 13 to 14) ? decimate-by-16: complex output (jmode 15 to 16) 7.3.5.4.2 ddc gain boost the ddc gain boost (see the ddc configuration register ) provides additional gain through the ddc block. setting boost to 1 sets the total decimation filter chain gain to 6.02 db. with a setting of 0, the total decimation filter chain has a 0-db gain. only use this setting when the negative image of the input signal is filtered out by the decimation filters, otherwise clipping may occur. there is no reduction in analog performance when gain boost is enabled or disabled, but care must be taken to understand the reference output power for proper performance calculations. advance information
44 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.6 jesd204b interface the ADC12DJ3200QML-SP uses the jesd204b high-speed serial interface for data converters to transfer data from the adc to the receiving logic device. the ADC12DJ3200QML-SP serialized lanes are capable of operating up to 12.8 gbps, slightly above the jesd204b maximum lane rate. a maximum of 16 lanes can be used to allow lower lane rates for interfacing with speed-limited logic devices. figure 21 shows a simplified block diagram of the jesd204b interface protocol. figure 21. simplified jesd204b interface diagram the various signals used in the jesd204b interface and the associated ADC12DJ3200QML-SP pin names are summarized briefly in table 16 for reference. table 16. summary of jesd204b signals signal name ADC12DJ3200QML-SP pin names description data da0+...da7+, da0 ? ...da7 ? , db0+...db7+, db0 ? ...db7 ? high-speed serialized data after 8b, 10b encoding sync syncse, tmstp+, tmstp ? link initialization signal (handshake), toggles low to start code group synchronization (cgs) process device clock clk+, clk ? adc sampling clock, also used for clocking digital logic and output serializers sysref sysref+, sysref ? system timing reference used to deterministically reset the internal local multiframe counters in each jesd204b device 7.3.6.1 transport layer the transport layer takes samples from the adc output (in decimation bypass mode) or from the ddc output and maps the samples into octets, frames, multiframes, and lanes. sample mapping is defined by the jesd204b mode that is used, defined by parameters such as l, m, f, s, n, n', cf, and so forth. there are a number of predefined transport layer modes in the ADC12DJ3200QML-SP that are defined in table 19 . the high level configuration parameters for the transport layer in the ADC12DJ3200QML-SP are described in table 17 . for simplicity, the transport layer mode is chosen by simply setting the jmode parameter and the desired k value. for reference, the various configuration parameters for jesd204b are defined in table 18 . 7.3.6.2 scrambler an optional data scrambler can be used to scramble the octets before transmission across the channel. scrambling is recommended in order to remove the possibility of spectral peaks in the transmitted data. the jesd204b receiver automatically synchronizes its descrambler to the incoming scrambled data stream. the initial lane alignment sequence (ila) is never scrambled. scrambling can be enabled by setting scr (in the jesd204b control register ). adc jesd204b transport layer scrambler (optional) jesd204b link layer jesd204b tx 8b/10b encoder application layer jesd204b transport layer descramble (optional) jesd204b link layer jesd204b rx 8b/10b decoder adc jesd204b block logic device jesd204b block analog channel advance information
45 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.6.3 link layer the link layer serves multiple purposes in jesd204b, including establishing the code boundaries (see the code group synchronization (cgs) section), initializing the link (see the initial lane alignment sequence (ilas) section), encoding the data (see the 8b, 10b encoding section), and monitoring the health of the link (see the frame and multiframe monitoring section). 7.3.6.3.1 code group synchronization (cgs) the first step in initializing the jesd204b link, after sysref is processed, is to achieve code group synchronization. the receiver first asserts the sync signal when ready to initialize the link. the transmitter responds to the request by sending a stream of k28.5 characters. the receiver then aligns its character clock to the k28.5 character sequence. code group synchronization is achieved after receiving four k28.5 characters successfully. the receiver deasserts sync on the next local multiframe clock (lmfc) edge after cgs is achieved and waits for the transmitter to start the initial lane alignment sequence. 7.3.6.3.2 initial lane alignment sequence (ilas) after the transmitter detects the sync signal deassert, the transmitter waits until its next lmfc edge to start sending the initial lane alignment sequence. the ilas consists of four multiframes each containing a predetermined sequence. the receiver searches for the start of the ilas to determine the frame and multiframe boundaries. as the ilas reaches the receiver for each lane, the lane starts to buffer its data until all receivers have received the ilas and subsequently release the ilas from all lanes at the same time in order to align the lanes. the second multiframe of the ilas contains configuration parameters for the jesd204b that can be used by the receiver to verify that the transmitter and receiver configurations match. 7.3.6.3.3 8b, 10b encoding the data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across the link using 8b, 10b encoding. 8b, 10b encoding provides dc balance for ac-coupling of the serdes links and a sufficient number of edge transitions for the receiver to reliably recover the data clock. 8b, 10b also provides some amount of error detection where a single bit error in a character likely results in either not being able to find the 10-bit character in the 8b, 10b decoder lookup table or incorrect character disparity. 7.3.6.3.4 frame and multiframe monitoring the ADC12DJ3200QML-SP supports frame and multiframe monitoring for verifying the health of the jesd204b link. if the last octet of a frame matches the last octet of the previous frame, then the last octet in the second frame is replaced with an /f/ (/k28.7/) character. if the second frame is the last frame of a multiframe, then an /a/ (/k28.3/) character is used instead. when scrambling is enabled, if the last octet of a frame is 0xfc then the transmitter replaces the octet with an /f/ (/k28.7/) character. with scrambling, if the last octet of a multiframe is 0x7c then the transmitter replaces the octet with an /a/ (/k28.3/) character. when the receiver detects an /f/ or /a/ character, the receiver checks if the character occurs at the end of a frame or multiframe, and replaces that octet with the appropriate data character. the receiver can report an error if the alignment characters occur in the incorrect place and trigger a link realignment. 7.3.6.4 physical layer the jesd204b physical layer consists of a current mode logic (cml) output driver and receiver. the receiver consists of a clock detection and recovery (cdr) unit to extract the data clock from the serialized data stream and can contain an equalizer to correct for the low-pass response of the physical transmission channel. likewise, the transmitter can contain pre-equalization to account for frequency dependent losses across the channel. the total reach of the serdes links depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error performance. the serdes lanes do not have to be matched in length because the receiver aligns the lanes during the initial lane alignment sequence. advance information
46 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.6.4.1 serdes pre-emphasis the ADC12DJ3200QML-SP high-speed output drivers can pre-equalize the transmitted data stream by using pre-emphasis in order to compensate for the low-pass response of the transmission channel. configurable pre- emphasis settings allow the output drive waveform to be optimized for different pcb materials and signal transmission distances. the pre-emphasis setting is adjusted through the serializer pre-emphasis setting ser_pe (in the serializer pre-emphasis control register ). higher values increase the pre-emphasis to compensate for more lossy pcb materials. this adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. adjust the pre-emphasis setting to optimize the eye-opening for the specific hardware configuration and line rates needed. 7.3.6.5 jesd204b enable the jesd204b interface must be disabled through jesd_en (in the jesd204b enable register ) while any of the other jesd204b parameters are being changed. when jesd_en is set to 0 the block is held in reset and the serializers are powered down. the clocks for this section are also gated off to further save power. when the parameters are set as desired, the jesd204b block can be enabled (jesd_en is set to 1). 7.3.6.6 multi-device synchronization and deterministic latency jesd204b subclass 1 outlines a method to achieve deterministic latency across the serial link. if two devices achieve the same deterministic latency then they can be considered synchronized. this latency must be achieved from system startup to startup to be deterministic. there are two key requirements to achieve deterministic latency. the first is proper capture of sysref for which the ADC12DJ3200QML-SP provides a number of features to simplify this requirement at giga-sample clock rates (see the sysref capture for multi- device synchronization and deterministic latency section for more information). the second requirement is to choose a proper elastic buffer release point in the receiver. because the ADC12DJ3200QML-SP is an adc, the ADC12DJ3200QML-SP is the transmitter (tx) in the jesd204b link and the logic device is the receiver (rx). the elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to the receiver. a proper release point is one that provides sufficient margin against delay variations. an incorrect release point results in a latency variation of one lmfc period. choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an lmfc edge, and the total expected delay variation for all devices. with this information the region of invalid release points within the lmfc period can be defined, which stretches from the minimum to maximum delay for all lanes. essentially, the designer must make certain that the data for all lanes arrives at all devices before the release point occurs. figure 22 illustrates a timing diagram that demonstrates this requirement. in this figure, the data for two adcs is shown. the second adc has a longer routing distance (t pcb ) and results in a longer link delay. first, the invalid region of the lmfc period is marked off as determined by the data arrival times for all devices. then, the release point is set by using the release buffer delay (rbd) parameter to shift the release point an appropriate number of frame clocks from the lmfc edge so that the release point occurs within the valid region of the lmfc cycle. in the case of figure 22 , the lmfc edge (rbd = 0) is a good choice for the release point because there is sufficient margin on each side of the valid region. figure 22. lmfc valid region definition for elastic buffer release point selection tx lmfc rx lmfc adc 1 data propagation t tx t pcb t rx-deser time adc 2 data propagation t tx t pcb invalid region of lmfc valid region of lmfc nominal link delay (arrival at elastic buffer) link delay variation choose lmfc edge as release point (rbd = 0) release point margin t rx-deser advance information
47 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated the tx and rx lmfcs do not necessarily need to be phase aligned, but knowledge of their phase is important for proper elastic buffer release point selection. also, the elastic buffer release point occurs within every lmfc cycle, but the buffers only release when all lanes have arrived. therefore, the total link delay can exceed a single lmfc period; see the jesd204b multi-device synchronization: breaking down the requirements techincal brief for more information. 7.3.6.7 operation in subclass 0 systems the ADC12DJ3200QML-SP can operate with subclass 0 compatibility provided that multi-adc synchronization and deterministic latency are not required. with these limitations, the device can operate without the application of sysref. the internal local multiframe clock is automatically self-generated with unknown timing. sync is used as normal to initiate the cgs and ila. 7.3.7 alarm monitoring a number of built-in alarms are available to monitor internal events. several types of alarms and upsets are detected by this feature: 1. serializer pll is not locked 2. jesd204b link is not transmitting data (not in the data transmission state) 3. sysref causes internal clocks to be realigned 4. an upset that impacts the internal clocks when an alarm occurs, a bit for each specific alarm is set in alm_status. each alarm bit remains set until the host system writes a 1 to clear the alarm. if the alarm type is not masked (see the alarm mask register ), then the alarm is also indicated by the alarm register. the calstat output pin can be configured as an alarm output that goes high when an alarm occurs; see the cal_status_sel bit in the calibration pin configuration register . 7.3.7.1 nco upset detection the nco_alm register bit indicates if the nco in channel a or b has been upset. the nco phase accumulators in channel a are continuously compared to channel b. if the accumulators differ for even one clock cycle, the nco_alm register bit is set and remains set until cleared by the host system by writing a 1. this feature requires the phase and frequency words for each nco accumulator in ddc a (phaseax, freqax) to be set to the same values as the nco accumulators in ddc b (phasebx, freqbx). for example, phasea0 must be the same as phaseb0 and freqa0 must be the same as freqb0, however, phasea1 can be set to a different value than phasea0. this requirement ultimately reduces the number of nco frequencies available for phase coherent frequency hopping from four to two for each ddc. ddc b can use a different nco frequency than ddc a by setting the ncob[1:0] pins to a different value than ncoa[1:0]. this detection is only valid after the ncos are synchronized by either sysref or the start of the ila sequence (as determined by the nco synchronization register ). for the nco upset detection to work properly, follow these steps: 1. program jesd_en = 0 2. make sure the device is configured to use both channels (pd_ach = 0, pd_bch = 0) 3. select a jmode that uses the nco 4. program all nco frequencies and phases to be the same for channel a and b (for example, freqa0 = freqb0, freqa1 = freqb1, freqa2 = freqb2, and freqa3 = freqb3) 5. if desired, use the cmode and csel registers or the ncoa[1:0] and ncob[1:0] pins to choose a unique frequency for channel a and channel b 6. program jesd_en = 1 7. synchronize the ncos (using the ila or using sysref); see nco phase synchronization 8. write a 1 to the nco_alm register bit to clear it 9. monitor the nco_alm status bit or the calstat output pin if cal_status_sel is properly configured 10. if the frequency or phase registers are changed while the nco is enabled, the ncos can get out of synchronization 11. repeat steps 7-9 12. if the device enters and exits global power down, repeat steps 7-9 advance information
48 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.7.2 clock upset detection the clk_alm register bit indicates if the internal clocks have been upset. the clocks in channel a are continuously compared to channel b. if the clocks differ for even one devclk / 2 cycle, the clk_alm register bit is set and remains set until cleared by the host system by writing a 1. for the clk_alm register bit to function properly, follow these steps: 1. program jesd_en = 0 2. make sure the part is configured to use both channels (pd_ach = 0, pd_bch = 0) 3. program jesd_en = 1 4. write clk_alm = 1 to clear clk_alm 5. monitor the clk_alm status bit or the calstat output pin if cal_status_sel is properly configured 6. when exiting global power-down (via mode or the pd pin), the clk_alm status bit may be set and must be cleared by writing a 1 to clk_alm 7.3.8 temperature monitoring diode a built-in thermal monitoring diode is made available on the tdiode+ and tdiode ? pins. this diode facilitates temperature monitoring and characterization of the device in higher ambient temperature environments. although the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the diode voltage slope provided in the electrical characteristics: dc specifications table. perform offset measurement with the device unpowered or with the pd pin asserted to minimize device self-heating. only assert the pd pin long enough to take the offset measurement. recommended monitoring devices include the lm95233 device and similar remote-diode temperature monitoring products from texas instruments. 7.3.9 analog reference voltage the reference voltage for the ADC12DJ3200QML-SP is derived from an internal band-gap reference. a buffered version of the reference voltage is available at the bg pin for user convenience. this output has an output- current capability of 100 a. the bg output must be buffered if more current is required. no provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale- range register settings. in unique cases, the va11 supply voltage can act as the reference voltage by setting bg_bypass (see the internal reference bypass register ). advance information
49 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes the ADC12DJ3200QML-SP can be configured to operate in a number of functional modes. these modes are described in this section. 7.4.1 dual-channel mode the ADC12DJ3200QML-SP can be used as a dual-channel adc where the sampling rate is equal to the clock frequency (f s = f clk ) provided at the clk+ and clk ? pins. the two inputs, ain and bin , serve as the respective inputs for each channel in this mode. this mode is chosen simply by setting jmode to the appropriate setting for the desired configuration as described in table 19 . the analog inputs can be swapped by setting dual_input (see the input mux control register ) 7.4.2 single-channel mode (des mode) the ADC12DJ3200QML-SP can also be used as a single-channel adc where the sampling rate is equal to two times the clock frequency (f s = 2 f clk ) provided at the clk+ and clk ? pins. this mode effectively interleaves the two adc channels together to form a single-channel adc at twice the sampling rate. this mode is chosen simply by setting jmode to the appropriate setting for the desired configuration as described in table 19 . either analog input, ina or inb , can serve as the input to the adc, however ina is recommended for best performance. the analog input can be selected using single_input (see the input mux control register ). the digital down-converters cannot be used in single-channel mode. note for optimized performance in single-channel mode, use ina as the input to the adc. 7.4.3 jesd204b modes the ADC12DJ3200QML-SP can be programmed as a single-channel or dual-channel adc, with or without decimation, and a number jesd204b output formats. table 17 summarizes the basic operating mode configuration parameters and whether they are user configured or derived. caution powering down high-speed data outputs (da0 ... da7 , db0 ... db7 ) for extended times can damage the output serializers, especially at high data rates. for information regarding reliable serializer operation, see the power-down modes section. table 17. ADC12DJ3200QML-SP operating mode configuration parameters parameter description user configured or derived value jmode jesd204b operating mode, automatically derives the rest of the jesd204b parameters, single-channel or dual-channel mode and the decimation factor user configured set by jmode (see the jesd204b mode register ) d decimation factor derived see table 19 des 1 = single-channel mode, 0 = dual-channel mode derived see table 19 r number of bits transmitted per lane per devclk cycle. the jesd204b line rate is the devclk frequency times r. this parameter sets the serdes pll multiplication factor or controls bypassing of the serdes pll. derived see table 19 links number of jesd204b links used derived see table 19 k number of frames per multiframe user configured set by km1 (see the jesd204b k parameter register ), see the allowed values in table 19 advance information
50 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated there are a number of parameters required to define the jesd204b format, all of which are sent across the link during the initial lane alignment sequence. in the ADC12DJ3200QML-SP, most parameters are automatically derived based on the selected jmode; however, a few are configured by the user. table 18 describes these parameters. table 18. jesd204b initial lane alignment sequence parameters parameter description user configured or derived value adjcnt lmfc adjustment amount (not applicable) derived always 0 adjdir lmfc adjustment direction (not applicable) derived always 0 bid bank id derived always 0 cf number of control words per frame derived always 0 cs control bits per sample derived always set to 0 in ilas, see table 19 for actual usage did device identifier, used to identify the link user configured set by did (see the jesd204b did parameter register ), see table 20 f number of octets (bytes) per frame (per lane) derived see table 19 hd high-density format (samples split between lanes) derived always 0 jesdv jesd204 standard revision derived always 1 k number of frames per multiframe user configured set by the km1 register, see the jesd204b k parameter register l number of serial output lanes per link derived see table 19 lid lane identifier for each lane derived see table 20 m number of converters used to determine lane bit packing; may not match number of adc channels in the device derived see table 19 n sample resolution (before adding control and tail bits) derived see table 19 n' bits per sample after adding control and tail bits derived see table 19 s number of samples per converter (m) per frame derived see table 19 scr scrambler enabled user configured set by the jesd204b control register subclassv device subclass version derived always 1 res1 reserved field 1 derived always 0 res2 reserved field 2 derived always 0 chksum checksum for ilas checking (sum of all above parameters modulo 256) derived computed based on parameters in this table configuring the ADC12DJ3200QML-SP is made easy by using a single configuration parameter called jmode (see the jesd204b mode register ). using table 19 , the correct jmode value can be found for the desired operating mode. the modes listed in table 19 are the only available operating modes. this table also gives a range and allowable step size for the k parameter (set by km1, see the jesd204b k parameter register ), which sets the multiframe length in number of frames. advance information
ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 51 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) m equals l in these modes to allow the samples to be sent in time-order over l lanes. the m parameter does not represent the actual number of converters. interleave the m sample streams from each link in the receiver to produce the correct sample data; see table 21 to table 38 for more details. (2) cs is always reported as 0 in the initial lane alignment sequence (ilas) for the ADC12DJ3200QML-SP. table 19. ADC12DJ3200QML-SP operating modes ADC12DJ3200QML-SP operating mode user-specified parameter derived parameters input clock range (mhz) jmode k [min:step:max] d des links n cs n ? l (per link) m (per link) f s r (fbit / fclk) 12-bit, single-channel, 8 lanes 0 3:1:32 1 1 2 12 0 12 4 4 (1) 8 5 4 800-3200 12-bit, single-channel, 16 lanes 1 3:1:32 1 1 2 12 0 12 8 8 (1) 8 5 2 800-3200 12-bit, dual-channel, 8 lanes 2 3:1:32 1 0 2 12 0 12 4 4 (1) 8 5 4 800-3200 12-bit, dual-channel, 16 lanes 3 3:1:32 1 0 2 12 0 12 8 8 (1) 8 5 2 800-3200 8-bit, single-channel, 4 lanes 4 18:2:32 1 1 2 8 0 8 2 1 1 2 5 800-2560 8-bit, single-channel, 8 lanes 5 18:2:32 1 1 2 8 0 8 4 1 1 4 2.5 800-3200 8-bit, dual-channel, 4 lanes 6 18:2:32 1 0 2 8 0 8 2 1 1 2 5 800-2560 8-bit, dual-channel, 8 lanes 7 18:2:32 1 0 2 8 0 8 4 1 1 4 2.5 800-3200 reserved 8 ? ? ? ? ? ? ? ? ? ? ? ? ? 15-bit, real data, decimate-by-2, 8 lanes 9 9:1:32 2 0 2 15 1 (2) 16 4 1 2 4 2.5 800-3200 15-bit, decimate-by-4, 4 lanes 10 9:1:32 4 0 2 15 1 (2) 16 2 2 2 1 5 800-2560 15-bit, decimate-by-4, 8 lanes 11 9:1:32 4 0 2 15 1 (2) 16 4 2 2 2 2.5 800-3200 12-bit, decimate-by-4, 16 lanes 12 3:1:32 4 0 2 12 0 12 8 8 (1) 8 5 1 1000-3200 15-bit, decimate-by-8, 2 lanes 13 5:1:32 8 0 2 15 1 (2) 16 1 2 4 1 5 800-2560 15-bit, decimate-by-8, 4 lanes 14 9:1:32 8 0 2 15 1 (2) 16 2 2 2 1 2.5 800-3200 15-bit, decimate-by-16, 1 lane 15 3:1:32 16 0 1 15 1 (2) 16 1 4 8 1 5 800-2560 15-bit, decimate-by-16, 2 lanes 16 5:1:32 16 0 2 15 1 (2) 16 1 2 4 1 2.5 800-3200 8-bit, single-channel, 16 lanes 17 18:2:32 1 1 2 8 0 8 8 1 1 8 1.25 800-3200 8-bit, dual-channel, 16 lanes 18 18:2:32 1 0 2 8 0 8 8 1 1 8 1.25 800-3200 advance information
52 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated the ADC12DJ3200QML-SP has a total of 16 high-speed output drivers that are grouped into two 8-lane jesd204b links. most operating modes use two links with up to eight lanes per link. the lanes and their derived configuration parameters are described in table 20 . for a specified jmode, the lowest indexed lanes for each link are used and the higher indexed lanes for each link are automatically powered down. always route the lowest indexed lanes to the logic device. table 20. ADC12DJ3200QML-SP lane assignment and parameters device pin designation link did (user configured) lid (derived) da0 a set by did (see the jesd204b did parameter register ), the effective did is equal to the did register setting (did) 0 da1 1 da2 2 da3 3 da4 4 da5 5 da6 6 da7 7 db0 b set by did (see the jesd204b did parameter register ), the effective did is equal to the did register setting plus 1 (did+1) 0 db1 1 db2 2 db3 3 db4 4 db5 5 db6 6 db7 7 7.4.3.1 jesd204b output data formats output data are formatted in a specific optimized fashion for each jmode setting. when the ddc is not used (decimation = 1) the 12-bit offset binary values are mapped into octets. for the ddc mode, the 16-bit values (15- bit complex data plus 1 overrange bit) are mapped into octets. the following tables show the specific mapping formats for a single frame. in all mappings the tail bits (t) are 0 (zero). in table 21 to table 38 , the single- channel format samples are defined as sn, where n is the sample number within the frame. in the dual-channel real output formats (ddc bypass and decimate-by-2), the samples are defined as an and bn, where an are samples from channel a and bn are samples from channel b. in the complex output formats (decimate-by-4, decimate-by-8, decimate-by-16), the samples are defined as ain, aqn, bin and bqn, where ain and aqn are the in-phase and quadrature-phase samples of channel a and bin and bqn are the in-phase and quadrature-phase samples of channel b. all samples are formatted as msb first, lsb last. advance information
53 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 21. jmode 0 (12-bit, decimate-by-1, single-channel, 8 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 s0 s8 s16 s24 s32 t da1 s2 s10 s18 s26 s34 t da2 s4 s12 s20 s28 s36 t da3 s6 s14 s22 s30 s38 t db0 s1 s9 s17 s25 s33 t db1 s3 s11 s19 s27 s35 t db2 s5 s13 s21 s29 s37 t db3 s7 s15 s23 s31 s39 t table 22. jmode 1 (12-bit, decimate-by-1, single-channel, 16 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 s0 s16 s32 s48 s64 t da1 s2 s18 s34 s50 s66 t da2 s4 s20 s36 s52 s68 t da3 s6 s22 s38 s54 s70 t da4 s8 s24 s40 s56 s72 t da5 s10 s26 s42 s58 s74 t da6 s12 s28 s44 s60 s76 t da7 s14 s30 s46 s62 s78 t db0 s1 s17 s33 s49 s65 t db1 s3 s19 s35 s51 s67 t db2 s5 s21 s37 s53 s69 t db3 s7 s23 s39 s55 s71 t db4 s9 s25 s41 s57 s73 t db5 s11 s27 s43 s59 s75 t db6 s13 s29 s45 s61 s77 t db7 s15 s31 s47 s63 s79 t table 23. jmode 2 (12-bit, decimate-by-1, dual-channel, 8 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 a0 a4 a8 a12 a16 t da1 a1 a5 a9 a13 a17 t da2 a2 a6 a10 a14 a18 t da3 a3 a7 a11 a15 a19 t db0 b0 b4 b8 b12 b16 t db1 b1 b5 b9 b13 b17 t db2 b2 b6 b10 b14 b18 t db3 b3 b7 b11 b15 b19 t advance information
54 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 24. jmode 3 (12-bit, decimate-by-1, dual-channel, 16 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 a0 a8 a16 a24 a32 t da1 a1 a9 a17 a25 a33 t da2 a2 a10 a18 a26 a34 t da3 a3 a11 a19 a27 a35 t da4 a4 a12 a20 a28 a36 t da5 a5 a13 a21 a29 a37 t da6 a6 a14 a22 a30 a38 t da7 a7 a15 a23 a31 a39 t db0 b0 b8 b16 b24 b32 t db1 b1 b9 b17 b25 b33 t db2 b2 b10 b18 b26 b34 t db3 b3 b11 b19 b27 b35 t db4 b4 b12 b20 b28 b36 t db5 b5 b13 b21 b29 b37 t db6 b6 b14 b22 b30 b38 t db7 b7 b15 b23 b31 b39 t table 25. jmode 4 (8-bit, decimate-by-1, single-channel, 4 lanes) octet 0 nibble 0 1 da0 s0 da1 s2 db0 s1 db1 s3 table 26. jmode 5 (8-bit, decimate-by-1, single-channel, 8 lanes) octet 0 nibble 0 1 da0 s0 da1 s2 da2 s4 da3 s6 db0 s1 db1 s3 db2 s5 db3 s7 table 27. jmode 6 (8-bit, decimate-by-1, dual-channel, 4 lanes) octet 0 nibble 0 1 da0 a0 da1 a1 db0 b0 db1 b1 advance information
55 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 28. jmode 7 (8-bit, decimate-by-1, dual-channel, 8 lanes) octet 0 nibble 0 1 da0 a0 da1 a1 da2 a2 da3 a3 db0 b0 db1 b1 db2 b2 db3 b3 table 29. jmode 9 (15-bit, decimate-by-2, dual-channel, 8 lanes) octet 0 1 nibble 0 1 2 3 da0 a0 da1 a1 da2 a2 da3 a3 db0 b0 db1 b1 db2 b2 db3 b3 table 30. jmode 10 (15-bit, decimate-by-4, dual-channel, 4 lanes) octet 0 1 nibble 0 1 2 3 da0 ai0 da1 aq0 db0 bi0 db1 bq0 table 31. jmode 11 (15-bit, decimate-by-4, dual-channel, 8 lanes) octet 0 1 nibble 0 1 2 3 da0 ai0 da1 ai1 da2 aq0 da3 aq1 db0 bi0 db1 bi1 db2 bq0 db3 bq1 advance information
56 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 32. jmode 12 (12-bit, decimate-by-4, dual-channel, 16 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 ai0 ai4 ai8 ai12 ai16 t da1 aq0 aq4 aq8 aq12 aq16 t da2 ai1 ai5 ai9 ai13 ai17 t da3 aq1 aq5 aq9 aq13 aq17 t da4 ai2 ai6 ai10 ai14 ai18 t da5 aq2 aq6 aq10 aq14 aq218 t da6 ai3 ai7 ai11 ai15 ai19 t da7 aq3 aq7 aq11 aq15 aq19 t db0 bi0 bi4 bi8 bi12 bi16 t db1 bq0 bq4 bq8 bq12 bq16 t db2 bi1 bi5 bi9 bi13 bi17 t db3 bq1 bq5 bq9 bq13 bq17 t db4 bi2 bi6 bi10 bi14 bi18 t db5 bq2 bq6 bq10 bq14 bq218 t db6 bi3 bi7 bi11 bi15 bi19 t db7 bq3 bq7 bq11 bq15 bq19 t table 33. jmode 13 (15-bit, decimate-by-8, dual-channel, 2 lanes) octet 0 1 2 3 nibble 0 1 2 3 4 5 6 7 da0 ai0 aq0 db0 bi0 bq0 table 34. jmode 14 (15-bit, decimate-by-8, dual-channel, 4 lanes) octet 0 1 nibble 0 1 2 3 da0 ai0 da1 aq0 db0 bi0 db1 bq0 table 35. jmode 15 (15-bit, decimate-by-16, dual-channel, 1 lane) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 ai0 aq0 bi0 bq0 table 36. jmode 16 (15-bit, decimate-by-16, dual-channel, 2 lanes) octet 0 1 2 3 nibble 0 1 2 3 4 5 6 7 da0 ai0 aq0 db0 bi0 bq0 advance information
57 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 37. jmode 17 (8-bit, decimate-by-1, single-channel, 16 lanes) octet 0 nibble 0 1 da0 s0 da1 s2 da2 s4 da3 s6 da4 s8 da5 s10 da6 s12 da7 s14 db0 s1 db1 s3 db2 s5 db3 s7 db4 s9 db5 s11 db6 s13 db7 s15 table 38. jmode 18 (8-bit, decimate-by-1, dual-channel, 16 lanes) octet 0 nibble 0 1 da0 a0 da1 a1 da2 a2 da3 a3 da4 a4 da5 a5 da6 a6 da7 a7 db0 b0 db1 b1 db2 b2 db3 b3 db4 b4 db5 b5 db6 b6 db7 b7 advance information
58 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.3.2 dual ddc and redundant data mode when operating in dual-channel mode, the data from one channel can be routed to both digital down-converter blocks by using dig_bind_a or dig_bind_b (see the digital channel binding register ). this feature enables down-conversion of two separate captured bands from a single adc channel. the second adc can be powered down in this mode by setting pd_ach or pd_bch (see the device configuration register ). additionally, dig_bind_a or dig_bind_b can be used to provide redundant data to separate digital processors by routing data from one adc channel to both jesd204b links. redundant data mode is available for all jmode modes except for the single-channel modes. both dual ddc mode and redundant data mode are demonstrated in figure 23 where the data for adc channel a is routed to both ddcs and then transmitted to a single processor or two processors (for redundancy). figure 23. dual ddc mode or redundant data mode for channel a mux dig_bind_a = 0 adc channel a adc channel b jesd204b link a (da0-da7) ddc a mux jmode ddc bypass mux jesd204b link b (db0-db7) ddc b mux jmode ddc bypass dig_bind_b = 0 . advance information
59 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.4 power-down modes the pd input pin allows the ADC12DJ3200QML-SP devices to be entirely powered down. power-down can also be controlled by mode (see the device configuration register ). the serial data output drivers are disabled when pd is high. when the device returns to normal operation, the jesd204 link must be re-established, and the adc pipeline and decimation filters contain meaningless information so the system must wait a sufficient time for the data to be flushed. if power-down for power savings is desired, the system must power down the supply voltages regulators for va19, va11, and vd11 rather than make use of the pd input or mode settings. caution powering down the high-speed data outputs (da0 ... da7 , db0 ... db7 ) for extended times may damage the output serializers, especially at high data rates. powering down the serializers occurs when the pd pin is held high, the mode register is programmed to a value other than 0x00 or 0x01, the pd_ach or pd_bch registers settings are programmed to 1, or when the jmode register setting is programmed to a mode that uses less than the 16 total lanes that the device allows. for instance, jmode 0 uses eight total lanes and therefore the four highest-indexed lanes for each jesd204b link (da4 ... da7 , db4 ... db7 ) are powered down in this mode. when the pd pin is held high or the mode register is programmed to a value other than 0x00 or 0x01, all output serializers are powered down. when the pd_ach or pd_bch register settings are programmed to 1, the associated adc channel and lanes are powered down. to prevent unreliable operation, the pd pin and mode register must only be used for brief periods of time to measure temperature diode offsets and not used for long-term power savings. furthermore, using a jmode that uses fewer than 16 lanes results in unreliable operation of the unused lanes. if the system will never use the unused lanes during the lifetime of the device, then the unused lanes do not cause issues and can be powered down. if the system may make use of the unused lanes at a later time, the reliable operation of the serializer outputs can be maintained by enabling jextra_a and jextra_b, which results in the vd11 power consumption to increase and the output serializers to toggle. advance information
60 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.5 test modes a number of device test modes are available. these modes insert known patterns of information into the device data path for assistance with system debug, development, or characterization. 7.4.5.1 serializer test-mode details test modes are enabled by setting jtest (see the jesd204b test pattern control register ) to the desired test mode. each test mode is described in detail in the following sections. regardless of the test mode, the serializer outputs are powered up based on jmode. only enable the test modes when the jesd204b link is disabled. figure 24 provides a diagram showing the various test mode insertion points. figure 24. test mode insertion points 7.4.5.2 prbs test modes the prbs test modes bypass the 8b, 10b encoder. these test modes produce pseudo-random bit streams that comply with the itu-t o.150 specification. these bit streams are used with lab test equipment that can self- synchronize to the bit pattern and, therefore, the initial phase of the pattern is not defined. the sequences are defined by a recursive equation. for example, equation 10 defines the prbs7 sequence. y[n] = y[n ? 6] y[n ? 7] where ? bit n is the xor of bit [n ? 6] and bit [n ? 7], which are previously transmitted bits (10) table 39 lists equations and sequence lengths for the available prbs test modes. the initial phase of the pattern is unique for each lane. table 39. pbrs mode equations prbs test mode sequence sequence length (bits) prbs7 y[n] = y[n ? 6] y[n ? 7] 127 prbs15 y[n] = y[n ? 14] y[n ? 15] 32767 prbs23 y[n] = y[n ? 18] y[n ? 23] 8388607 7.4.5.3 ramp test mode in the ramp test mode, the jesd204b link layer operates normally, but the transport layer is disabled and the input from the formatter is ignored. after the ila sequence, each lane transmits an identical octet stream that increments from 0x00 to 0xff and repeats. adc jesd204b transport layer scrambler (optional) jesd204b link layer jesd204b tx 8b/10b encoder adc jesd204b block long/short transport octet ramp test mode enable repeated ila modified rpat test mode enable prbs d21.5 k28.5 serial outputs high/low test mode enable active lanes and serial rates set by jmode advance information
61 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.5.4 short and long transport test mode jesd204b defines both short and long transport test modes to verify that the transport layers in the transmitter and receiver are operating correctly. the ADC12DJ3200QML-SP has three different transport layer test patterns depending on the n' value of the specified jmode (see table 19 ). 7.4.5.4.1 short transport test pattern short transport test patterns send a predefined octet format that repeats every frame. in the adc12dj3200qml- sp, all jmode configurations that have an n' value of 8 or 12 use the short transport test pattern. table 40 and table 41 define the short transport test patterns for n' values of 8 and 12. all applicable lanes are shown, however only the enabled lanes (lowest indexed) for the configured jmode are used. table 40. short transport test pattern for n ' = 8 modes (length = 2 frames) frame 0 1 da0 0x00 0xff da1 0x01 0xfe da2 0x02 0xfd da3 0x03 0xfc db0 0x00 0xff db1 0x01 0xfe db2 0x02 0xfd db3 0x03 0xfc table 41. short transport test pattern for n ' = 12 modes (length = 1 frame) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 0xf01 0xf02 0xf03 0xf04 0xf05 t da1 0xe11 0xe12 0xe13 0xe14 0xe15 t da2 0xd21 0xd22 0xd23 0xd24 0xd25 t da3 0xc31 0xc32 0xc33 0xc34 0xc35 t da4 0xb41 0xb42 0xb43 0xb44 0xb45 t da5 0xa51 0xa52 0xa53 0xa54 0xa55 t da6 0x961 0x962 0x963 0x964 0x965 t da7 0x871 0x872 0x873 0x874 0x875 t db0 0xf01 0xf02 0xf03 0xf04 0xf05 t db1 0xe11 0xe12 0xe13 0xe14 0xe15 t db2 0xd21 0xd22 0xd23 0xd24 0xd25 t db3 0xc31 0xc32 0xc33 0xc34 0xc35 t db4 0xb41 0xb42 0xb43 0xb44 0xb45 t db5 0xa51 0xa52 0xa53 0xa54 0xa55 t db6 0x961 0x962 0x963 0x964 0x965 t db7 0x871 0x872 0x873 0x874 0x875 t advance information
62 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.5.4.2 long transport test pattern the long-transport test mode is used in all of the jmode modes where n' equals 16. patterns are generated in accordance with the jesd204b standard and are different for each output format as defined in table 19 . the rules for the pattern are defined below. equation 11 gives the length of the test pattern. the long transport test pattern is the same for link a and link b, where dax lanes belong to link a and dbx lanes belong to link b. long test pattern length (frames) = k ceil[(m s + 2) / k] (11) ? sample data: ? frame 0: each sample contains n bits, with all samples set to the converter id (cid) plus 1 (cid + 1). the cid is defined based on the converter number within the link; two links are used in all modes except jmode 15. within a link, the converters are numbered by channel (a or b) and in-phase (i) and quadrature-phase (q) and reset between links. for instance, in jmode 10, two links are used so channel a and b data are separated into separate links and the in-phase component for each channel has cid = 0 and the quadrature-phase component has cid = 1. in jmode 15, one link is used, so channel a and b are within the same link and ai has cid = 0, aq has cid = 1, bi has cid = 2, and bq has cid = 3. ? frame 1: each sample contains n bits, with each sample (for each converter) set as its individual sample id (sid) within the frame plus 1 (sid + 1) ? frame 2 +: each sample contains n bits, with the data set to 2 n ? 1 for all samples (for example, if n is 15 then 2 n ? 1 = 16384) ? control bits (if cs > 0): ? frame 0 to m s ? 1: the control bit belonging to the sample mod (i, s) of the converter floor (i, s) is set to 1 and all others are set to 0, where i is the frame index (i = 0 is the first frame of the pattern). essentially, the control bit walks from the lowest indexed sample to the highest indexed sample and from the lowest indexed converter to the highest indexed converter, changing position every frame. ? frame m s +: all control bits are set to 0 table 42 describes an example long transport test pattern for when jmode = 10, k = 10. table 42. example long transport test pattern (jmode = 10, k = 10) time pattern repeats octet num 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 da0 0x0003 0x0002 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0003 da1 0x0004 0x0003 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 db0 0x0003 0x0002 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0003 db1 0x0004 0x0003 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 frame n frame n + 1 frame n + 2 frame n + 3 frame n + 4 frame n + 5 frame n + 6 frame n + 7 frame n + 8 frame n + 9 frame n + 10 the pattern starts at the end of the initial lane alignment sequence (ilas) and repeats indefinitely as long as the link remains running. for more details see the jesd204b specification, section 5.1.6.3. advance information
63 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.5.5 d21.5 test mode in this test mode, the controller transmits a continuous stream of d21.5 characters (alternating 0s and 1s). 7.4.5.6 k28.5 test mode in this test mode, the controller transmits a continuous stream of k28.5 characters. 7.4.5.7 repeated ila test mode in this test mode, the jesd204b link layer operates normally, except that the ila sequence (ilas) repeats indefinitely instead of starting the data phase. whenever the receiver issues a synchronization request, the transmitter initiates code group synchronization. upon completion of code group synchronization, the transmitter repeatedly transmits the ila sequence. 7.4.5.8 modified rpat test mode a 12-octet repeating pattern is defined in incits tr-35-2004. the purpose of this pattern is to generate white spectral content for jesd204b compliance and jitter testing. table 43 lists the pattern before and after 8b, 10b encoding. table 43. modified rpat pattern values octet number dx.y notation 8-bit input to 8b, 10b encoder 20b output of 8b, 10b encoder (two characters) 0 d30.5 0xbe 0x86ba6 1 d23.6 0xd7 2 d3.1 0x23 0xc6475 3 d7.2 0x47 4 d11.3 0x6b 0xd0e8d 5 d15.4 0x8f 6 d19.5 0xb3 0xca8b4 7 d20.0 0x14 8 d30.2 0x5e 0x7949e 9 d27.7 0xfb 10 d21.1 0x35 0xaa665 11 d25.2 0x59 advance information
64 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.6 calibration modes and trimming the ADC12DJ3200QML-SP has two calibration modes available: foreground calibration and background calibration. when foreground calibration is initiated the adcs are automatically taken offline and the output data becomes mid-code (0x000 in 2's complement) while a calibration is occurring. background calibration allows the adc to continue normal operation while the adc cores are calibrated in the background by swapping in a different adc core to take its place. additional offset calibration features are available in both foreground and background calibration modes. further, a number of adc parameters can be trimmed to optimize performance in a user system. the ADC12DJ3200QML-SP consists of a total of six sub-adcs, each referred to as a bank , with two banks forming an adc core. the banks sample out-of-phase so that each adc core is two-way interleaved. the six banks form three adc cores, referred to as adc a, adc b, and adc c. in foreground calibration mode, adc a samples ina and adc b samples inb in dual-channel mode and both adc a and adc b sample ina (or inb ) in single-channel mode. in the background calibration modes, the third adc core, adc c, is swapped in periodically for adc a and adc b so that they can be calibrated without disrupting operation. figure 25 illustrates a diagram of the calibration system including labeling of the banks that make up each adc core. when calibration is performed the linearity, gain, and offset voltage for each bank are calibrated to an internally generated calibration signal. the analog inputs can be driven during calibration, both foreground and background, except that when offset calibration (os_cal or bgos_cal) is used there must be no signals (or aliased signals) near dc for proper estimation of the offset (see the offset calibration section). figure 25. ADC12DJ3200QML-SP calibration system block diagram in addition to calibration, a number of adc parameters are user controllable to provide trimming for optimal performance. these parameters include input offset voltage, adc gain, interleaving timing, and input termination resistance. the default trim values are programmed at the factory to unique values for each device that are determined to be optimal at the test system operating conditions. the user can read the factory-programmed values from the trim registers and adjust as desired. the register fields that control the trimming are labeled adc a ina+ ina inb+ inb calibration signal calibration signal calibration signal bank 1 bank 0 adc c bank 3 bank 2 adc b bank 5 bank 4 calibration engine mux mux mux mux mux adc a output adc b output calibration engine calibration engine calibration engine calibration engine interleave interleave interleave advance information
65 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated according to the input that is being sampled (ina or inb ), the bank that is being trimmed, or the adc core that is being trimmed. the user is not expected to change the trim values as operating conditions change, however optimal performance can be obtained by doing so. any custom trimming must be done on a per device basis because of process variations, meaning that there is no global optimal setting for all parts. see the trimming section for information about the available trim parameters and associated registers. 7.4.6.1 foreground calibration mode foreground calibration requires the adc to stop converting the analog input signals during the procedure. foreground calibration always runs on power-up and the user must wait a sufficient time before programming the device to make sure that the calibration is finished. foreground calibration can be initiated by triggering the calibration engine. the trigger source can be either the cal_trig pin or cal_soft_trig (see the calibration software trigger register ) and is chosen by setting cal_trig_en (see the calibration pin configuration register ). 7.4.6.2 background calibration mode background calibration mode allows the adc to continuously operate, with no interruption of data. this continuous operation is accomplished by activating an extra adc core that is calibrated and then takes over operation for one of the other previously active adc cores. when that adc core is taken offline, that adc is calibrated and can in turn take over to allow the next adc to be calibrated. this process operates continuously, making sure that the adc cores always provide the optimum performance regardless of system operating condition changes. because of the additional active adc core, background calibration mode has increased power consumption in comparison to foreground calibration mode. the low-power background calibration (lpbg) mode discussed in the low-power background calibration (lpbg) mode section provides reduced average power consumption in comparison with the standard background calibration mode. background calibration can be enabled by setting cal_bg (see the calibration configuration 0 register ). cal_trig_en must be set to 0 and cal_soft_trig must be set to 1. great care has been taken to minimize effects on converted data as the core switching process occurs; however, small brief glitches may still occur on the converter data as the cores are swapped. 7.4.6.3 low-power background calibration (lpbg) mode low-power background calibration (lpbg) mode reduces the power-overhead of enabling additional adc cores. off-line cores are powered down until ready to be calibrated and put on-line. set lp_en = 1 to enable the low- power background calibration feature. lp_sleep_dly is used to adjust the amount of time an adc sleeps before waking up for calibration (if lp_en = 1 and lp_trig = 0). lp_wake_dly sets how long the core is allowed to stabilize before calibration and being put on-line. lp_trig is used to select between an automatic switching process or one that is controlled by the user via cal_soft_trig or cal_trig. in this mode there is an increase in power consumption during the adc core calibration. the power consumption roughly alternates between the power consumption in foreground calibration when the spare adc core is sleeping to the power consumption in background calibration when the spare adc is being calibrated. design the power-supply network to handle the transient power requirements for this mode. advance information
66 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.7 offset calibration foreground calibration and background calibration modes inherently calibrate the offsets of the adc cores; however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the standard calibration process. in both dual-channel mode and single-channel mode, uncalibrated input buffer offsets result in a shift in the mid-code output (dc offset) with no input. further, in single-channel mode uncalibrated input buffer offsets can result in a fixed spur at f s / 2. a separate calibration is provided to correct the input buffer offsets. there must be no signals at or near dc, or aliased signals that fall at or near dc, in order to properly calibrate the offsets. these input signals must not exist during normal operation, or the system must be designed to mute the input signal during calibration. foreground offset calibration is enabled using cal_os and only performs the calibration one time as part of the foreground calibration procedure. background offset calibration is enabled via cal_bgos and continues to correct the offset as part of the background calibration routine to account for operating condition changes. when cal_bgos is set, the system must make sure that there are no dc or near- dc signals or aliased signals that fall at or near dc during normal operation. offset calibration can be performed as a foreground operation when using background calibration by setting cal_os to 1 before setting cal_en, but does not correct for variations as operating conditions change. the offset calibration correction uses the input offset voltage trim registers (see table 44 ) to correct the offset and therefore must not be written by the user when offset calibration is used. the user can read the calibrated values by reading the oadj_x_viny registers, where x is the adc core and y is the input (ina or inb ), after calibration is completed. only read the values when fg_done is read as 1 when using foreground offset calibration (cal_os = 1) and do not read the values when using background offset calibration (cal_bgos = 1). advance information
67 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4.8 trimming table 44 lists the parameters that can be trimmed and the associated registers. table 44. trim register descriptions trim parameter trim register notes band-gap reference bg_trim measurement on bg output pin. input termination resistance rtrim_x, where x = a for ina or b for inb ) the device must be powered on with a clock applied. input offset voltage oadj_x_viny, where x = adc core (a, b or c) and y = a for ina or b for inb ) a different trim value is allowed for each adc core (a, b, or c) to allow more consistent offset performance in background calibration mode. ina and inb gain gain_trim_x, where x = a for ina or b for inb ) set fs_range_a and fs_range_b to default values before trimming the input. use fs_range_a and fs_range_b to adjust the full-scale input voltage. ina and inb full-scale input voltage fs_range_x, where x = a for ina or b for inb ) full-scale input voltage adjustment for each input. the default value is effected by gain_trim_x (x = a or b). trim gain_trim_x with fs_range_x set to the default value. fs_range_x can then be used to trim the full-scale input voltage. intra-adc core timing (bank timing) bx_time_y, where x = bank number (0 ? 5) and y = 0 or ? 90 clock phase trims the timing between the two banks of an adc core (adc a, b, or c) for two clock phases, either 0 or ? 90 . the ? 90 clock phase is used in single-channel mode only. inter-adc core timing (dual-channel mode) tadj_a, tadj_b, tadj_ca, tadj_cb the suffix letter (a, b, ca, or cb) indicates the adc core that is being trimmed. ca indicates the timing trim in background calibration mode for adc c when standing in for adc a, whereas cb is the timing trim for adc c when standing in for adc b. inter-adc core timing (single-channel mode) tadj_a_fg90, tadj_b_fg0, tadj_a_bg90, tadj_c_bg0, tadj_c_bg90, tadj_b_bg0 the middle letter (a, b, or c) indicates the adc core that is being trimmed. fg indicates a trim for foreground calibration while bg indicates background calibration. the suffix of 0 or 90 indicates the clock phase applied to the adc core. 0 indicates a 0 clock and is sampling in-phase with the clock input. 90 indicates a 90 clock and therefore is sampling out-of-phase with the clock input. these timings must be trimmed for optimal performance if the user prefers to use inb in single-channel mode. these timings are trimmed for ina at the factory. 7.4.9 offset filtering the ADC12DJ3200QML-SP has an additional feature that can be enabled to reduce offset-related interleaving spurs at f s / 2 and f s / 4 (single input mode only). offset filtering is enabled via cal_osfilt. the osfilt_bw and osfilt_soak parameters can be adjusted to tradeoff offset spur reduction with potential impact on information in the mission mode signal being processed. set these two parameters to the same value under most situations. the dc_restore setting is used to either retain or filter out all dc-related content in the signal. advance information
68 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5 programming 7.5.1 using the serial interface the serial interface is accessed using the following four pins: serial clock (sclk), serial data in (sdi), serial data out (sdo), and serial interface chip-select ( scs). register access is enabled through the scs pin. 7.5.1.1 scs this signal must be asserted low to access a register through the serial interface. setup and hold times with respect to the sclk must be observed. 7.5.1.2 sclk serial data input is accepted at the rising edge of this signal. sclk has no minimum frequency requirement. 7.5.1.3 sdi each register access requires a specific 24-bit pattern at this input. this pattern consists of a read-and-write (r/w) bit, register address, and register value. the data are shifted in msb first and multi-byte registers are always in little-endian format (least significant byte stored at the lowest address). setup and hold times with respect to the sclk must be observed (see the timing requirements table). 7.5.1.4 sdo the sdo signal provides the output data requested by a read command. this output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles. as shown in figure 26 , each register access consists of 24 bits. the first bit is high for a read and low for a write. the next 15 bits are the address of the register that is to be written to. during write operations, the last eight bits are the data written to the addressed register. during read operations, the last eight bits on sdi are ignored and, during this time, the sdo outputs the data from the addressed register. figure 26 shows the serial protocol details. figure 26. serial interface protocol: single read/write sclk 1 24 single register access scs sdi command field data field sdo (read mode) data field high z high z 17 16 8 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/w advance information
69 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) 7.5.1.5 streaming mode the serial interface supports streaming reads and writes. in this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. additional clock cycles of write or read data are immediately transferred, as long as the scs input is maintained in the asserted (logic low) state. the register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming transaction. the addr_asc bit (register 000h, bits 5 and 2) controls whether the address value ascends (increments) or descends (decrements). streaming mode can be disabled by setting the addr_hold bit (see the user spi configuration register ). figure 27 shows the streaming mode transaction details. figure 27. serial interface protocol: streaming read and write see the register maps section for detailed information regarding the registers. note the serial interface must not be accessed during adc calibration. accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. writing or reading the serial registers also reduces dynamic adc performance for the duration of the register access time. sclk 1 24 multiple register access scs sdi command field data field (write mode) sdo (read mode) data field high z 17 16 8 32 data field high z 25 data field (write mode) a14 a13 a12 a1 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/w d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 advance information
70 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6 register maps memory map lists all the ADC12DJ3200QML-SP registers. memory map address reset acronym type register name standard spi-3.0 (0x000 to 0x00f) 0x000 0x30 config_a r/w configuration a register 0x001 undefined reserved r reserved 0x002 0x00 device_config r/w device configuration register 0x003 0x03 chip_type r chip type register 0x004-0x005 0x0020 chip_id r chip id registers 0x006 0x0a chip_version r chip version register 0x007-0x00b undefined reserved r reserved 0x00c-0x00d 0x0451 vendor_id r vendor identification register 0x00e-0x00f undefined reserved r reserved user spi configuration (0x010 to 0x01f) 0x010 0x00 usr0 r/w user spi configuration register 0x011-0x01f undefined reserved r reserved miscellaneous analog registers (0x020 to 0x047) 0x020-0x028 undefined reserved r reserved 0x029 0x00 clk_ctrl0 r/w clock control register 0 0x02a 0x20 clk_ctrl1 r/w clock control register 1 0x02b undefined reserved r reserved 0x02c-0x02e undefined sysref_pos r sysref capture position register 0x02f undefined reserved r reserved 0x030-0x031 0xa000 fs_range_a r/w ina full-scale range adjust register 0x032-0x033 0xa000 fs_range_b r/w inb full-scale range adjust register 0x034-0x037 undefined reserved r reserved 0x038 0x00 bg_bypass r/w internal reference bypass register 0x039-0x03a undefined reserved r reserved 0x03b 0x00 tmstp_ctrl r/w tmstp control register 0x03c-0x047 undefined reserved r reserved serializer registers (0x048 to 0x05f) 0x048 0x00 ser_pe r/w serializer pre-emphasis control register 0x049-0x05f undefined reserved r reserved calibration registers (0x060 to 0x0ff) 0x060 0x01 input_mux r/w input mux control register 0x061 0x01 cal_en r/w calibration enable register 0x062 0x01 cal_cfg0 r/w calibration configuration 0 register 0x063-0x069 undefined reserved r reserved 0x06a undefined cal_status r calibration status register 0x06b 0x00 cal_pin_cfg r/w calibration pin configuration register 0x06c 0x01 cal_soft_trig r/w calibration software trigger register 0x06d undefined reserved r reserved 0x06e 0x88 cal_lp r/w low-power background calibration register 0x06f undefined reserved r reserved 0x070 0x00 cal_data_en r/w calibration data enable register 0x071 undefined cal_data r/w calibration data register 0x072-0x079 undefined reserved r reserved advance information
71 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated register maps (continued) memory map (continued) address reset acronym type register name 0x07a undefined gain_trim_a r/w channel a gain trim register 0x07b undefined gain_trim_b r/w channel b gain trim register 0x07c undefined bg_trim r/w band-gap reference trim register 0x07d undefined reserved r reserved 0x07e undefined rtrim_a r/w vina input resistor trim register 0x07f undefined rtrim_b r/w vinb input resistor trim register 0x080 undefined tadj_a_fg90 r/w timing adjustment for a-adc, single-channel mode, foreground calibration register 0x081 undefined tadj_b_fg0 r/w timing adjustment for b-adc, single-channel mode, foreground calibration register 0x082 undefined tadj_a_bg90 r/w timing adjustment for a-adc, single-channel mode, background calibration register 0x083 undefined tadj_c_bg0 r/w timing adjustment for c-adc, single-channel mode, background calibration register 0x084 undefined tadj_c_bg90 r/w timing adjustment for c-adc, single-channel mode, background calibration register 0x085 undefined tadj_b_bg0 r/w timing adjustment for b-adc, single-channel mode, background calibration register 0x086 undefined tadj_a r/w timing adjustment for a-adc, dual-channel mode register 0x087 undefined tadj_ca r/w timing adjustment for c-adc acting for a-adc, dual- channel mode register 0x088 undefined tadj_cb r/w timing adjustment for c-adc acting for b-adc, dual- channel mode register 0x089 undefined tadj_b r/w timing adjustment for b-adc, dual-channel mode register 0x08a-0x08b undefined oadj_a_ina r/w offset adjustment for a-adc and ina register 0x08c-0x08d undefined oadj_a_inb r/w offset adjustment for a-adc and inb register 0x08e-0x08f undefined oadj_c_ina r/w offset adjustment for c-adc and ina register 0x090-0x091 undefined oadj_c_inb r/w offset adjustment for c-adc and inb register 0x092-0x093 undefined oadj_b_ina r/w offset adjustment for b-adc and ina register 0x094-0x095 undefined oadj_b_inb r/w offset adjustment for b-adc and inb register 0x096 undefined reserved r reserved 0x097 0x00 osfilt0 r/w offset filtering control 0 0x098 0x33 osfilt1 r/w offset filtering control 1 0x099-0x0ff undefined reserved r reserved adc bank registers (0x100 to 0x15f) 0x100-0x101 undefined reserved r reserved 0x102 undefined b0_time_0 r/w timing adjustment for bank 0 (0 clock) register 0x103 undefined b0_time_90 r/w timing adjustment for bank 0 ( ? 90 clock) register 0x104-0x111 undefined reserved r reserved 0x112 undefined b1_time_0 r/w timing adjustment for bank 1 (0 clock) register 0x113 undefined b1_time_90 r/w timing adjustment for bank 1 ( ? 90 clock) register 0x114-0x121 undefined reserved r reserved 0x122 undefined b2_time_0 r/w timing adjustment for bank 2 (0 clock) register 0x123 undefined b2_time_90 r/w timing adjustment for bank 2 ( ? 90 clock) register 0x124-0x131 undefined reserved r reserved 0x132 undefined b3_time_0 r/w timing adjustment for bank 3 (0 clock) register 0x133 undefined b3_time_90 r/w timing adjustment for bank 3 ( ? 90 clock) register 0x134-0x141 undefined reserved r reserved advance information
72 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated register maps (continued) memory map (continued) address reset acronym type register name 0x142 undefined b4_time_0 r/w timing adjustment for bank 4 (0 clock) register 0x143 undefined b4_time_90 r/w timing adjustment for bank 4 ( ? 90 clock) register 0x144-0x151 undefined reserved r reserved 0x152 undefined b5_time_0 r/w timing adjustment for bank 5 (0 clock) register 0x153 undefined b5_time_90 r/w timing adjustment for bank 5 ( ? 90 clock) register 0x154-0x15f undefined reserved r reserved lsb control registers (0x160 to 0x1ff) 0x160 0x00 enc_lsb r/w lsb control bit output register 0x161-0x1ff undefined reserved r reserved jesd204b registers (0x200 to 0x20f) 0x200 0x01 jesd_en r/w jesd204b enable register 0x201 0x02 jmode r/w jesd204b mode (jmode) register 0x202 0x1f km1 r/w jesd204b k parameter register 0x203 0x01 jsync_n r/w jesd204b manual sync request register 0x204 0x02 jctrl r/w jesd204b control register 0x205 0x00 jtest r/w jesd204b test pattern control register 0x206 0x00 did r/w jesd204b did parameter register 0x207 0x00 fchar r/w jesd204b frame character register 0x208 undefined jesd_status r/w jesd204b, system status register 0x209 0x00 pd_ch r/w jesd204b channel power-down 0x20a 0x00 jextra_a r/w jesd204b extra lane enable (link a) 0x20b 0x00 jextra_b r/w jesd204b extra lane enable (link b) 0x20c-0x20f undefined reserved r reserved digital down converter registers (0x210-0x2af) 0x210 0x00 ddc_cfg r/w ddc configuration register 0x211 0xf2 ovr_t0 r/w overrange threshold 0 register 0x212 0xab ovr_t1 r/w overrange threshold 1 register 0x213 0x07 ovr_cfg r/w overrange configuration register 0x214 0x00 cmode r/w ddc configuration preset mode register 0x215 0x00 csel r/w ddc configuration preset select register 0x216 0x02 dig_bind r/w digital channel binding register 0x217-0x218 0x0000 nco_rdiv r/w rational nco reference divisor register 0x219 0x02 nco_sync r/w nco synchronization register 0x21a-0x21f undefined reserved r reserved 0x220-0x223 0xc0000000 freqa0 r/w nco frequency (ddc a preset 0) 0x224-0x225 0x0000 phasea0 r/w nco phase (ddc a preset 0) 0x226-0x227 undefined reserved r reserved 0x228-0x22b 0xc0000000 freqa1 r/w nco frequency (ddc a preset 1) 0x22c-0x22d 0x0000 phasea1 r/w nco phase (ddc a preset 1) 0x22e-0x22f undefined reserved r reserved 0x230-0x233 0xc0000000 freqa2 r/w nco frequency (ddc a preset 2) 0x234-0x235 0x0000 phasea2 r/w nco phase (ddc a preset 2) 0x236-0x237 undefined reserved r reserved 0x238-0x23b 0xc0000000 freqa3 r/w nco frequency (ddc a preset 3) 0x23c-0x23d 0x0000 phasea3 r/w nco phase (ddc a preset 3) 0x23e-0x23f undefined reserved r reserved advance information
73 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated register maps (continued) memory map (continued) address reset acronym type register name 0x240-0x243 0xc0000000 freqb0 r/w nco frequency (ddc b preset 0) 0x244-0x245 0x0000 phaseb0 r/w nco phase (ddc b preset 0) 0x246-0x247 undefined reserved r reserved 0x248-0x24b 0xc0000000 freqb1 r/w nco frequency (ddc b preset 1) 0x24c-0x24d 0x0000 phaseb1 r/w nco phase (ddc b preset 1) 0x24e-0x24f undefined reserved r reserved 0x250-0x253 0xc0000000 freqb2 r/w nco frequency (ddc b preset 2) 0x254-0x255 0x0000 phaseb2 r/w nco phase (ddc b preset 2) 0x256-0x257 undefined reserved r reserved 0x258-0x25b 0xc0000000 freqb3 r/w nco frequency (ddc b preset 3) 0x25c-0x25d 0x0000 phaseb3 r/w nco phase (ddc b preset 3) 0x25e-0x296 undefined reserved r reserved 0x297 undefined spin_id r spin identification value 0x298-0x2af undefined reserved r reserved sysref calibration registers (0x2b0 to 0x2bf) 0x2b0 0x00 src_en r/w sysref calibration enable register 0x2b1 0x05 src_cfg r/w sysref calibration configuration register 0x2b2-0x2b4 undefined src_status r sysref calibration status 0x2b5-0x2b7 0x00 tad r/w devclk aperture delay adjustment register 0x2b8 0x00 tad_ramp r/w devclk timing adjust ramp control register 0x2b9-0x2bf undefined reserved r reserved alarm registers (0x2c0 to 0x2c2) 0x2c0 undefined alarm r alarm interrupt status register 0x2c1 0x1f alm_status r/w alarm status register 0x2c2 0x1f alm_mask r/w alarm mask register advance information
74 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1 register descriptions 7.6.1.1 standard spi-3.0 (0x000 to 0x00f) table 45. standard spi-3.0 registers address reset acronym register name section 0x000 0x30 config_a configuration a register configuration a register (address = 0x000) [reset = 0x30] 0x001 undefined reserved reserved ? 0x002 0x00 device_config device configuration register device configuration register (address = 0x002) [reset = 0x00] 0x003 0x03 chip_type chip type register chip type register (address = 0x003) [reset = 0x03] 0x004-0x005 0x0020 chip_id chip id registers chip id register (address = 0x004 to 0x005) [reset = 0x0020] 0x006 0x0a chip_version chip version register chip version register (address = 0x006) [reset = 0x01] 0x007-0x00b undefined reserved reserved ? 0x00c-0x00d 0x0451 vendor_id vendor identification register vendor identification register (address = 0x00c to 0x00d) [reset = 0x0451] 0x00e-0x00f undefined reserved reserved ? 7.6.1.1.1 configuration a register (address = 0x000) [reset = 0x30] figure 28. configuration a register (config_a) 7 6 5 4 3 2 1 0 soft_reset reserved addr_asc sdo_active reserved r/w-0 r-0 r/w-1 r-1 r-0000 table 46. config_a field descriptions bit field type reset description 7 soft_reset r/w 0 setting this bit results in a full reset of the device. this bit is self- clearing. after writing this bit, the device may take up to 750 ns to reset. during this time, do not perform any spi transactions. 6 reserved r 0 reserved 5 addr_asc r/w 1 0: descend ? decrement address while streaming reads/writes 1: ascend ? increment address while streaming reads/writes (default) 4 sdo_active r 1 always returns 1, indicating that the device always uses 4-wire spi mode. 3-0 reserved r 0000 reserved advance information
75 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.1.2 device configuration register (address = 0x002) [reset = 0x00] figure 29. device configuration register (device_config) 7 6 5 4 3 2 1 0 reserved mode r-0000 00 r/w-00 table 47. device_config field descriptions bit field type reset description 7-2 reserved r 0000 00 reserved 1-0 mode r/w 00 the spi 3.0 specification lists 1 as the low-power functional mode, 2 as the low-power fast resume, and 3 as power-down. this device does not support these modes. 0: normal operation ? full power and full performance (default) 1: normal operation ? full power and full performance 2: power down - everything is powered down. only use this setting for brief periods of time to calibrate the on-chip temperature diode measurement. see the recommended operating conditions table for more information. 3: power down - everything is powered down. only use this setting for brief periods of time to calibrate the on-chip temperature diode measurement. see the recommended operating conditions table for more information. 7.6.1.1.3 chip type register (address = 0x003) [reset = 0x03] figure 30. chip type register (chip_type) 7 6 5 4 3 2 1 0 reserved chip_type r-0000 r-0011 table 48. chip_type field descriptions bit field type reset description 7-4 reserved r 0000 reserved 3-0 chip_type r 0011 always returns 0x3, indicating that the device is a high-speed adc. 7.6.1.1.4 chip id register (address = 0x004 to 0x005) [reset = 0x0020] figure 31. chip id register (chip_id) 15 14 13 12 11 10 9 8 chip_id[15:8] r-0x00h 7 6 5 4 3 2 1 0 chip_id[7:0] r-0x20h table 49. chip_id field descriptions bit field type reset description 15-0 chip_id r 0x0020h always returns 0x0020, indicating that this device is an ADC12DJ3200QML-SP device. advance information
76 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.1.5 chip version register (address = 0x006) [reset = 0x01] figure 32. chip version register (chip_version) 7 6 5 4 3 2 1 0 chip_version r-0000 1010 table 50. chip_version field descriptions bit field type reset description 7-0 chip_version r 0000 1010 chip version, returns 0x0a. 7.6.1.1.6 vendor identification register (address = 0x00c to 0x00d) [reset = 0x0451] figure 33. vendor identification register (vendor_id) 15 14 13 12 11 10 9 8 vendor_id[15:8] r-0x04h 7 6 5 4 3 2 1 0 vendor_id[7:0] r-0x51h table 51. vendor_id field descriptions bit field type reset description 15-0 vendor_id r 0x0451h always returns 0x0451 (ti vendor id). 7.6.1.2 user spi configuration (0x010 to 0x01f) table 52. user spi configuration registers address reset acronym register name section 0x010 0x00 usr0 user spi configuration register user spi configuration register (address = 0x010) [reset = 0x00] 0x011-0x01f undefined reserved reserved ? 7.6.1.2.1 user spi configuration register (address = 0x010) [reset = 0x00] figure 34. user spi configuration register (usr0) 7 6 5 4 3 2 1 0 reserved addr_hold r-0000 000 r/w-0 table 53. usr0 field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 addr_hold r/w 0 0: use the addr_asc bit to define what happens to the address during streaming (default) 1: address remains static throughout streaming operation; this setting is useful for reading/writing calibration vector information at the cal_data register advance information
77 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.3 miscellaneous analog registers (0x020 to 0x047) table 54. miscellaneous analog registers address reset acronym register name section 0x020-0x028 undefined reserved reserved ? 0x029 0x00 clk_ctrl0 clock control register 0 clock control register 0 (address = 0x029) [reset = 0x00] 0x02a 0x20 clk_ctrl1 clock control register 1 clock control register 1 (address = 0x02a) [reset = 0x00] 0x02b undefined reserved reserved ? 0x02c-0x02e undefined sysref_pos sysref capture position register sysref capture position register (address = 0x02c- 0x02e) [reset = undefined] 0x02f undefined reserved reserved ? 0x030-0x031 0xa000 fs_range_a ina full-scale range adjust register ina full-scale range adjust register (address = 0x030- 0x031) [reset = 0xa000] 0x032-0x033 0xa000 fs_range_b inb full-scale range adjust register inb full-scale range adjust register (address = 0x032- 0x033) [reset = 0xa000] 0x034-0x037 undefined reserved reserved ? 0x038 0x00 bg_bypass internal reference bypass register internal reference bypass register (address = 0x038) [reset = 0x00] 0x039-0x03a undefined reserved reserved ? 0x03b 0x00 sync_ctrl tmstp control register tmstp control register (address = 0x03b) [reset = 0x00] 0x03c-0x047 undefined reserved reserved ? 7.6.1.3.1 clock control register 0 (address = 0x029) [reset = 0x00] figure 35. clock control register 0 (clk_ctrl0) 7 6 5 4 3 2 1 0 reserved sysref_proc_en sysref_recv_en sysref_zoom sysref_sel r/w-0 r/w-0 r/w-0 r/w-0 r/w-0000 table 55. clk_ctrl0 field descriptions bit field type reset description 7 reserved r/w 0 reserved 6 sysref_proc_en r/w 0 this bit enables the sysref processor. this bit must be set to allow the device to process sysref events. sysref_recv_en must be set before setting sysref_proc_en. 5 sysref_recv_en r/w 0 set this bit to enable the sysref receiver circuit. 4 sysref_zoom r/w 0 set this bit to zoom in the sysref strobe status (affects sysref_pos). 3-0 sysref_sel r/w 0000 set this field to select which sysref delay to use. set this field based on the results returned by sysref_pos. set this field to 0 to use sysref calibration. advance information
78 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.3.2 clock control register 1 (address = 0x02a) [reset = 0x00] figure 36. clock control register 1 (clk_ctrl1) 7 6 5 4 3 2 1 0 reserved devclk_lvpecl_en sysref_lvpecl_en sysref_inverted r/w-0010 0 r/w-0 r/w-0 r/w-0 table 56. clk_ctrl1 field descriptions bit field type reset description 7-3 reserved r/w 0010 0 reserved 2 devclk_lvpecl_en r/w 0 activate low-voltage pecl mode for devclk. 1 sysref_lvpecl_en r/w 0 activate low-voltage pecl mode for sysref. 0 sysref_inverted r/w 0 inverts the sysref signal used for alignment. 7.6.1.3.3 sysref capture position register (address = 0x02c-0x02e) [reset = undefined] figure 37. sysref capture position register (sysref_pos) 23 22 21 20 19 18 17 16 sysref_pos[23:16] r-undefined 15 14 13 12 11 10 9 8 sysref_pos[15:8] r-undefined 7 6 5 4 3 2 1 0 sysref_pos[7:0] r-undefined table 57. sysref_pos field descriptions bit field type reset description 23-0 sysref_pos r undefined this field returns a 24-bit status value that indicates the position of the sysref edge with respect to devclk. use this field to program sysref_sel. 7.6.1.3.4 ina full-scale range adjust register (address = 0x030-0x031) [reset = 0xa000] figure 38. ina full-scale range adjust register (fs_range_a) 15 14 13 12 11 10 9 8 fs_range_a[15:8] r/w-0xa0h 7 6 5 4 3 2 1 0 fs_range_a[7:0] r/w-0x00h table 58. fs_range_a field descriptions bit field type reset description 15-0 fs_range_a r/w 0xa000h this field enables adjustment of the analog full-scale range for ina. 0x0000: settings below 0x2000 may result in degraded device performance 0x2000: 500 mv pp - recommended minimum setting 0xa000: 800 mv pp (default) 0xffff: 1000 mv pp advance information
79 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.3.5 inb full-scale range adjust register (address = 0x032-0x033) [reset = 0xa000] figure 39. inb full scale range adjust register (fs_range_b) 15 14 13 12 11 10 9 8 fs_range_b[15:8] r/w-0xa0 7 6 5 4 3 2 1 0 fs_range_b[7:0] r/w-0x00 table 59. fs_range_b field descriptions bit field type reset description 15-0 fs_range_b r/w 0xa000h this field enables adjustment of the analog full-scale range for inb. 0x0000: settings below 0x2000 may result in degraded device performance 0x2000: 500 mv pp - recommended minimum setting 0xa000: 800 mv pp (default) 0xffff: 1000 mv pp 7.6.1.3.6 internal reference bypass register (address = 0x038) [reset = 0x00] figure 40. internal reference bypass register (bg_bypass) 7 6 5 4 3 2 1 0 reserved bg_bypass r/w-0000 000 r/w-0 table 60. bg_bypass field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 bg_bypass r/w 0 when set, va11 is used as the voltage reference instead of the internal reference. 7.6.1.3.7 tmstp control register (address = 0x03b) [reset = 0x00] figure 41. tmstp control register (tmstp_ctrl) 7 6 5 4 3 2 1 0 reserved tmstp_lvpecl_en tmstp_recv_en r/w-0000 00 r/w-0 r/w-0 table 61. tmstp_ctrl field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 tmstp_lvpecl_en r/w 0 when set, this bit activates the low-voltage pecl mode for the differential tmstp input. 0 tmstp_recv_en r/w 0 this bit enables the differential tmstp input. advance information
80 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.4 serializer registers (0x048 to 0x05f) table 62. serializer registers address reset acronym register name section 0x048 0x00 ser_pe serializer pre-emphasis control register serializer pre-emphasis control register (address = 0x048) [reset = 0x00] 0x049-0x05f undefined reserved reserved ? 7.6.1.4.1 serializer pre-emphasis control register (address = 0x048) [reset = 0x00] figure 42. serializer pre-emphasis control register (ser_pe) 7 6 5 4 3 2 1 0 reserved ser_pe r/w-0000 r/w-0000 table 63. ser_pe field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-0 ser_pe r/w 0000 this field sets the pre-emphasis for the serial lanes to compensate for the low-pass response of the pcb trace. this setting is a global setting that affects all 16 lanes. advance information
81 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5 calibration registers (0x060 to 0x0ff) table 64. calibration registers address reset acronym register name section 0x060 0x01 input_mux input mux control register input mux control register (address = 0x060) [reset = 0x01] 0x061 0x01 cal_en calibration enable register calibration enable register (address = 0x061) [reset = 0x01] 0x062 0x01 cal_cfg0 calibration configuration 0 register calibration configuration 0 register (address = 0x062) [reset = 0x01] 0x063-0x069 undefined reserved reserved ? 0x06a undefined cal_status calibration status register calibration status register (address = 0x06a) [reset = undefined] 0x06b 0x00 cal_pin_cfg calibration pin configuration register calibration pin configuration register (address = 0x06b) [reset = 0x00] 0x06c 0x01 cal_soft_trig calibration software trigger register calibration software trigger register (address = 0x06c) [reset = 0x01] 0x06d undefined reserved reserved ? 0x06e 0x88 cal_lp low-power background calibration register low-power background calibration register (address = 0x06e) [reset = 0x88] 0x06f undefined reserved reserved ? 0x070 0x00 cal_data_en calibration data enable register calibration data enable register (address = 0x070) [reset = 0x00] 0x071 undefined cal_data calibration data register calibration data register (address = 0x071) [reset = undefined] 0x072-0x079 undefined reserved reserved ? 0x07a undefined gain_trim_a channel a gain trim register channel a gain trim register (address = 0x07a) [reset = undefined] 0x07b undefined gain_trim_b channel b gain trim register channel b gain trim register (address = 0x07b) [reset = undefined] 0x07c undefined bg_trim band-gap reference trim register band-gap reference trim register (address = 0x07c) [reset = undefined] 0x07d undefined reserved reserved ? 0x07e undefined rtrim_a vina input resistor trim register vina input resistor trim register (address = 0x07e) [reset = undefined] 0x07f undefined rtrim_b vinb input resistor trim register vinb input resistor trim register (address = 0x07f) [reset = undefined] 0x080 undefined tadj_a_fg90 timing adjustment for a-adc, single-channel mode, foreground calibration register timing adjust for a-adc, single-channel mode, foreground calibration register (address = 0x080) [reset = undefined] 0x081 undefined tadj_b_fg0 timing adjustment for b-adc, single-channel mode, foreground calibration register timing adjust for b-adc, single-channel mode, foreground calibration register (address = 0x081) [reset = undefined] 0x082 undefined tadj_a_bg90 timing adjustment for a-adc, single-channel mode, background calibration register timing adjust for a-adc, single-channel mode, background calibration register (address = 0x082) [reset = undefined] 0x083 undefined tadj_c_bg0 timing adjustment for c-adc, single-channel mode, background calibration register timing adjust for c-adc, single-channel mode, background calibration register (address = 0x084) [reset = undefined] 0x084 undefined tadj_c_bg90 timing adjustment for c-adc, single-channel mode, background calibration register timing adjust for c-adc, single-channel mode, background calibration register (address = 0x084) [reset = undefined] 0x085 undefined tadj_b_bg0 timing adjustment for b-adc, single-channel mode, background calibration register timing adjust for b-adc, single-channel mode, background calibration register (address = 0x085) [reset = undefined] 0x086 undefined tadj_a timing adjustment for a-adc, dual- channel mode register timing adjust for a-adc, dual-channel mode register (address = 0x086) [reset = undefined] 0x087 undefined tadj_ca timing adjustment for c-adc acting for a-adc, dual-channel mode register timing adjust for c-adc acting for a-adc, dual-channel mode register (address = 0x087) [reset = undefined] 0x088 undefined tadj_cb timing adjustment for c-adc acting for b-adc, dual-channel mode register timing adjust for c-adc acting for b-adc, dual-channel mode register (address = 0x088) [reset = undefined] advance information
82 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 64. calibration registers (continued) address reset acronym register name section 0x089 undefined tadj_b timing adjustment for b-adc, dual- channel mode register timing adjust for b-adc, dual-channel mode register (address = 0x089) [reset = undefined] 0x08a-0x08b undefined oadj_a_ina offset adjustment for a-adc and ina register offset adjustment for a-adc and ina register (address = 0x08a-0x08b) [reset = undefined] 0x08c-0x08d undefined oadj_a_inb offset adjustment for a-adc and inb register offset adjustment for a-adc and inb register (address = 0x08c-0x08d) [reset = undefined] 0x08e-0x08f undefined oadj_c_ina offset adjustment for c-adc and ina register offset adjustment for c-adc and ina register (address = 0x08e-0x08f) [reset = undefined] 0x090-0x091 undefined oadj_c_inb offset adjustment for c-adc and inb register offset adjustment for c-adc and inb register (address = 0x090-0x091) [reset = undefined] 0x092-0x093 undefined oadj_b_ina offset adjustment for b-adc and ina register offset adjustment for b-adc and ina register (address = 0x092-0x093) [reset = undefined] 0x094-0x095 undefined oadj_b_inb offset adjustment for b-adc and inb register offset adjustment for b-adc and inb register (address = 0x094-0x095) [reset = undefined] 0x096 undefined reserved reserved ? 0x097 0x00 0sfilt0 offset filtering control 0 offset filtering control 0 register (address = 0x097) [reset = 0x00] 0x098 0x33 osfilt1 offset filtering control 1 offset filtering control 1 register (address = 0x098) [reset = 0x33] 0x099-0x0ff undefined reserved reserved ? 7.6.1.5.1 input mux control register (address = 0x060) [reset = 0x01] figure 43. input mux control register (input_mux) 7 6 5 4 3 2 1 0 reserved dual_input reserved single_input r/w-000 r/w-0 r/w-00 r/w-01 table 65. input_mux field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4 dual_input r/w 0 this bit selects inputs for dual-channel modes. if jmode is selecting a single-channel mode, this register has no effect. 0: a channel samples ina, b channel samples inb (no swap, default) 1: a channel samples inb, b channel samples ina (swap) 3-2 reserved r/w 00 reserved 1-0 single_input r/w 01 thid field defines which input is sampled in single-channel mode. if jmode is not selecting a single-channel mode, this register has no effect. 0: reserved 1: ina is used (default) 2: inb is used 3: reserved advance information
83 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.2 calibration enable register (address = 0x061) [reset = 0x01] figure 44. calibration enable register (cal_en) 7 6 5 4 3 2 1 0 reserved cal_en r/w-0000 000 r/w-1 table 66. cal_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 cal_en r/w 1 calibration enable. set this bit high to run calibration. set this bit low to hold the calibration in reset to program new calibration settings. clearing cal_en also resets the clock dividers that clock the digital block and jesd204b interface. some calibration registers require clearing cal_en before making any changes. all registers with this requirement contain a note in their descriptions. after changing the registers, set cal_en to re-run calibration with the new settings. always set cal_en before setting jesd_en. always clear jesd_en before clearing cal_en. 7.6.1.5.3 calibration configuration 0 register (address = 0x062) [reset = 0x01] only change this register when cal_en is 0. figure 45. calibration configuration 0 register (cal_cfg0) 7 6 5 4 3 2 1 0 reserved cal_osfilt cal_bgos cal_os cal_bg cal_fg r/w-000 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 table 67. cal_cfg0 field descriptions bit field type reset description 7-5 reserved r/w 0000 reserved 4 cal_osfilt r/w 0 enable offset filtering by setting this bit high. 3 cal_bgos r/w 0 0 : disables background offset calibration (default) 1: enables background offset calibration (requires cal_bg to be set). 2 cal_os r/w 0 0 : disables foreground offset calibration (default) 1: enables foreground offset calibration (requires cal_fg to be set) 1 cal_bg r/w 0 0 : disables background calibration (default) 1: enables background calibration 0 cal_fg r/w 1 0 : resets calibration values, skips foreground calibration 1: resets calibration values, then runs foreground calibration (default) advance information
84 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.4 calibration status register (address = 0x06a) [reset = undefined] figure 46. calibration status register (cal_status) 7 6 5 4 3 2 1 0 reserved cal_stopped fg_done r r r table 68. cal_status field descriptions bit field type reset description 7-2 reserved r reserved 1 cal_stopped r this bit returns a 1 when the background calibration has successfully stopped at the requested phase. this bit returns a 0 when calibration starts operating again. if background calibration is disabled, this bit is set when foreground calibration is completed or skipped. 0 fg_done r this bit is set high when the foreground calibration completes. 7.6.1.5.5 calibration pin configuration register (address = 0x06b) [reset = 0x00] figure 47. calibration pin configuration register (cal_pin_cfg) 7 6 5 4 3 2 1 0 reserved cal_status_sel cal_trig_en r/w-0000 0 r/w-00 r/w-0 table 69. cal_pin_cfg field descriptions bit field type reset description 7-3 reserved r/w 0000 0 reserved 2-1 cal_status_sel r/w 00 0: calstat output pin matches fg_done 1: reserved 2: calstat output pin matches alarm 3: calstat output pin is always low 0 cal_trig_en r/w 0 choose the hardware or software trigger source with this bit. 0: use the cal_soft_trig register for the calibration trigger; the cal_trig input is disabled (ignored) 1: use the cal_trig input for the calibration trigger; the cal_soft_trig register is ignored 7.6.1.5.6 calibration software trigger register (address = 0x06c) [reset = 0x01] figure 48. calibration software trigger register (cal_soft_trig) 7 6 5 4 3 2 1 0 reserved cal_soft_trig r/w-0000 000 r/w-1 table 70. cal_soft_trig field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 cal_soft_trig r/w 1 cal_soft_trig is a software bit to provide functionality of the cal_trig input. program cal_trig_en = 0 to use cal_soft_trig for the calibration trigger. if no calibration trigger is needed, leave cal_trig_en = 0 and cal_soft_trig = 1 (trigger is set high). advance information
85 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.7 low-power background calibration register (address = 0x06e) [reset = 0x88] figure 49. low-power background calibration register (cal_lp) 7 6 5 4 3 2 1 0 lp_sleep_dly lp_wake_dly reserved lp_trig lp_en r/w-010 r/w-01 r/w-0 r/w-0 r/w-0 table 71. cal_lp field descriptions bit field type reset description 7-5 lp_sleep_dly r/w 010 adjust how long an adc sleeps before waking up for calibration (only applies when lp_en = 1 and lp_trig = 0). values below 4 are not recommended because of limited overall power reduction benefits. 0: sleep delay = (2 3 + 1) 256 t devclk 1: sleep delay = (2 15 + 1) 256 t devclk 2: sleep delay = (2 18 + 1) 256 t devclk 3: sleep delay = (2 21 + 1) 256 t devclk 4: sleep delay = (2 24 + 1) 256 t devclk : default is approximately 1338 ms with a 3.2-ghz clock 5: sleep delay = (2 27 + 1) 256 t devclk 6: sleep delay = (2 30 + 1) 256 t devclk 7: sleep delay = (2 33 + 1) 256 t devclk 4-3 lp_wake_dly r/w 01 adjust how much time is given up for settling before calibrating an adc after wake-up (only applies when lp_en = 1). values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins. 0:wake delay = (2 3 + 1) 256 t devclk 1: wake delay = (2 18 + 1) 256 t devclk : default is approximately 21 ms with a 3.2-ghz clock 2: wake delay = (2 21 + 1) 256 t devclk 3: wake delay = (2 24 + 1) 256 t devclk 2 reserved r/w 0 reserved 1 lp_trig r/w 0 0: adc sleep duration is set by lp_sleep_dly (autonomous mode) 1: adcs sleep until woken by a trigger; an adc is awoken when the calibration trigger (cal_soft_trig bit or cal_trig input) is low 0 lp_en r/w 0 0: disables low-power background calibration (default) 1: enables low-power background calibration (only applies when cal_bg = 1) 7.6.1.5.8 calibration data enable register (address = 0x070) [reset = 0x00] figure 50. calibration data enable register (cal_data_en) 7 6 5 4 3 2 1 0 reserved cal_data_en r/w-0000 000 r/w-0 table 72. cal_data_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 cal_data_en r/w 0 set this bit to enable the cal_data register to enable reading and writing of calibration data; see the calibration data register for more information. advance information
86 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.9 calibration data register (address = 0x071) [reset = undefined] figure 51. calibration data register (cal_data) 7 6 5 4 3 2 1 0 cal_data r/w table 73. cal_data field descriptions bit field type reset description 7-0 cal_data r/w undefined after setting cal_data_en, repeated reads of this register return all calibration values for the adcs. repeated writes of this register input all calibration values for the adcs. to read the calibration data, read the register 673 times. to write the vector, write the register 673 times with previously stored calibration data. to speed up the read/write operation, set addr_hold = 1 and use the streaming read or write process. accessing the cal_data register when cal_stopped = 0 corrupts the calibration. also, stopping the process before reading or writing 673 times leaved the calibration data in an invalid state. 7.6.1.5.10 channel a gain trim register (address = 0x07a) [reset = undefined] figure 52. channel a gain trim register (gain_trim_a) 7 6 5 4 3 2 1 0 gain_trim_a r/w table 74. gain_trim_a field descriptions bit field type reset description 7-0 gain_trim_a r/w undefined this register enables gain trim of channel a. after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.5.11 channel b gain trim register (address = 0x07b) [reset = undefined] figure 53. channel b gain trim register (gain_trim_b) 7 6 5 4 3 2 1 0 gain_trim_b r/w table 75. gain_trim_b field descriptions bit field type reset description 7-0 gain_trim_b r/w undefined this register enables gain trim of channel b. after reset, the factory-trimmed value can be read and adjusted as required. advance information
87 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.12 band-gap reference trim register (address = 0x07c) [reset = undefined] figure 54. band-gap reference trim register (bg_trim) 7 6 5 4 3 2 1 0 reserved bg_trim r/w-0000 r/w table 76. bg_trim field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-0 bg_trim r/w undefined this register enables the internal band-gap reference to be trimmed. after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.5.13 vina input resistor trim register (address = 0x07e) [reset = undefined] figure 55. vina input resistor trim register (rtrim_a) 7 6 5 4 3 2 1 0 rtrim r/w table 77. rtrim_a field descriptions bit field type reset description 7-0 rtrim_a r/w undefined this register controls the vina adc input termination trim. after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.5.14 vinb input resistor trim register (address = 0x07f) [reset = undefined] figure 56. vinb input resistor trim register (rtrim_b) 7 6 5 4 3 2 1 0 rtrim r/w table 78. rtrim_b field descriptions bit field type reset description 7-0 rtrim_b r/w undefined this register controls the vinb adc input termination trim. after reset, the factory-trimmed value can be read and adjusted as required. advance information
88 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.15 timing adjust for a-adc, single-channel mode, foreground calibration register (address = 0x080) [reset = undefined] figure 57. register (tadj_a_fg90) 7 6 5 4 3 2 1 0 tadj_a_fg90 r/w table 79. tadj_a_fg90 field descriptions bit field type reset description 7-0 tadj_a_fg90 r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.16 timing adjust for b-adc, single-channel mode, foreground calibration register (address = 0x081) [reset = undefined] figure 58. register (tadj_b_fg0) 7 6 5 4 3 2 1 0 tadj_b_fg0 r/w table 80. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_b_fg0 r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.17 timing adjust for a-adc, single-channel mode, background calibration register (address = 0x082) [reset = undefined] figure 59. register (tadj_a_bg90) 7 6 5 4 3 2 1 0 tadj_a_bg90 r/w table 81. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_a_bg90 r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. advance information
89 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.18 timing adjust for c-adc, single-channel mode, background calibration register (address = 0x083) [reset = undefined] figure 60. timing adjust for c-adc, single-channel mode, background calibration register (tadj_c_bg0) 7 6 5 4 3 2 1 0 tadj_c_bg0 r/w table 82. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_c_bg0 r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.19 timing adjust for c-adc, single-channel mode, background calibration register (address = 0x084) [reset = undefined] figure 61. timing adjust for c-adc, single-channel mode, background calibration register (tadj_c_bg90) 7 6 5 4 3 2 1 0 tadj_c_bg90 r/w table 83. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_c_bg90 r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.20 timing adjust for b-adc, single-channel mode, background calibration register (address = 0x085) [reset = undefined] figure 62. timing adjust for b-adc, single-channel mode, background calibration register (tadj_b_bg0) 7 6 5 4 3 2 1 0 tadj_b_bg0 r/w table 84. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_b_bg0 r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. advance information
90 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.21 timing adjust for a-adc, dual-channel mode register (address = 0x086) [reset = undefined] figure 63. timing adjust for a-adc, dual-channel mode register (tadj_a) 7 6 5 4 3 2 1 0 tadj_a r/w table 85. tadj_a field descriptions bit field type reset description 7-0 tadj_a r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.22 timing adjust for c-adc acting for a-adc, dual-channel mode register (address = 0x087) [reset = undefined] figure 64. timing adjust for c-adc acting for a-adc, dual-channel mode register (tadj_ca) 7 6 5 4 3 2 1 0 tadj_ca r/w table 86. tadj_ca field descriptions bit field type reset description 7-0 tadj_ca r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.23 timing adjust for c-adc acting for b-adc, dual-channel mode register (address = 0x088) [reset = undefined] figure 65. timing adjust for c-adc acting for b-adc, dual-channel mode register (tadj_cb) 7 6 5 4 3 2 1 0 tadj_cb r/w table 87. tadj_cb field descriptions bit field type reset description 7-0 tadj_cb r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. advance information
91 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.24 timing adjust for b-adc, dual-channel mode register (address = 0x089) [reset = undefined] figure 66. timing adjust for b-adc, dual-channel mode register (tadj_b) 7 6 5 4 3 2 1 0 tadj_b r/w table 88. tadj_b field descriptions bit field type reset description 7-0 tadj_b r/w undefined this register (and other subsequent tadj* registers) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory- trimmed value can be read and adjusted as required. 7.6.1.5.25 offset adjustment for a-adc and ina register (address = 0x08a-0x08b) [reset = undefined] figure 67. offset adjustment for a-adc and ina register (oadj_a_ina) 15 14 13 12 11 10 9 8 reserved oadj_a_ina[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_a_ina[7:0] r/w table 89. oadj_a_ina field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_a_ina r/w undefined offset adjustment value for adc0 (a-adc) applied when adc0 samples ina. the format is unsigned. after reset, the factory- trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os = 1 and cal_bgos = 0, only read oadj* registers if fg_done = 1 ? if cal_bg = 1 and cal_bgos = 1, only read oadj* register if cal_stopped = 1 advance information
92 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.26 offset adjustment for a-adc and inb register (address = 0x08c-0x08d) [reset = undefined] figure 68. offset adjustment for a-adc and inb register (oadj_a_inb) 15 14 13 12 11 10 9 8 reserved oadj_a_inb[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_a_inb[7:0] r/w table 90. oadj_a_inb field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_a_inb r/w undefined offset adjustment value for adc0 (a-adc) applied when adc0 samples inb. the format is unsigned. after reset, the factory- trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os = 1 and cal_bgos = 0, only read oadj* registers if fg_done = 1 ? if cal_bg = 1 and cal_bgos = 1, only read oadj* register if cal_stopped = 1 7.6.1.5.27 offset adjustment for c-adc and ina register (address = 0x08e-0x08f) [reset = undefined] figure 69. offset adjustment for c-adc and ina register (oadj_c_ina) 15 14 13 12 11 10 9 8 reserved oadj_c_ina[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_c_ina[7:0] r/w table 91. oadj_c_ina field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_c_ina r/w undefined offset adjustment value for adc1 (a-adc) applied when adc1 samples ina. the format is unsigned. after reset, the factory- trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os = 1 and cal_bgos = 0, only read oadj* registers if fg_done = 1 ? if cal_bg = 1 and cal_bgos = 1, only read oadj* register if cal_stopped = 1 advance information
93 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.28 offset adjustment for c-adc and inb register (address = 0x090-0x091) [reset = undefined] figure 70. offset adjustment for c-adc and inb register (oadj_c_inb) 15 14 13 12 11 10 9 8 reserved oadj_c_inb[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_c_inb[7:0] r/w table 92. oadj_c_inb field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_c_inb r/w undefined offset adjustment value for adc1 (a-adc) applied when adc1 samples inb. the format is unsigned. after reset, the factory- trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os = 1 and cal_bgos = 0, only read oadj* registers if fg_done = 1 ? if cal_bg = 1 and cal_bgos = 1, only read oadj* register if cal_stopped = 1 7.6.1.5.29 offset adjustment for b-adc and ina register (address = 0x092-0x093) [reset = undefined] figure 71. offset adjustment for b-adc and ina register (oadj_b_ina) 15 14 13 12 11 10 9 8 reserved oadj_b_ina[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_b_ina[7:0] r/w table 93. oadj_b_ina field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_b_ina r/w undefined offset adjustment value for adc2 (b-adc) applied when adc2 samples ina. the format is unsigned. after reset, the factory- trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os = 1 and cal_bgos = 0, only read oadj* registers if fg_done = 1 ? if cal_bg = 1 and cal_bgos = 1, only read oadj* register if cal_stopped = 1 advance information
94 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.30 offset adjustment for b-adc and inb register (address = 0x094-0x095) [reset = undefined] figure 72. offset adjustment for b-adc and inb register (oadj_b_inb) 15 14 13 12 11 10 9 8 reserved oadj_b_inb[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_b_inb[7:0] r/w table 94. oadj_b_inb field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_b_inb r/w undefined offset adjustment value for adc2 (b-adc) applied when adc2 samples inb. the format is unsigned. after reset, the factory- trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os = 1 and cal_bgos=0, only read oadj* registers if fg_done = 1 ? if cal_bg = 1 and cal_bgos=1, only read oadj* register if cal_stopped = 1 7.6.1.5.31 offset filtering control 0 register (address = 0x097) [reset = 0x00] figure 73. offset filtering control 0 register (osfilt0) 7 6 5 4 3 2 1 0 reserved dc_restore r/w-0000 000 r/w table 95. osfilt0 field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 dc_restore r/w 0 when set, the offset filtering feature (enabled by cal_osfilt) filters only the offset mismatch across adc banks and does not remove the frequency content near dc. when cleared, the feature filters all offsets from all banks, thus filtering all dc content in the signal; see the offset filtering section. advance information
95 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.5.32 offset filtering control 1 register (address = 0x098) [reset = 0x33] figure 74. offset filtering control 1 register (osfilt1) 7 6 5 4 3 2 1 0 osfilt_bw osfilt_soak r/w-0011 r/w-0011 table 96. osfilt1 field descriptions bit field type reset description 7-4 osfilt_bw r/w 0011 this field adjusts the iir filter bandwidth for the offset filtering feature (enabled by cal_osfilt). more bandwidth suppresses more flicker noise from the adcs and reduces the offset spurs. less bandwidth minimizes the impact of the filters on the mission mode signal. osfilt_bw: iir coefficient: ? 3-db bandwidth (single sided) 0: reserved 1: 2 -10 : 609e-9 f devclk 2: 2 -11 : 305e-9 f devclk 3: 2 -12 : 152e-9 f devclk 4: 2 -13 : 76e-9 f devclk 5: 2 -14 : 38e-9 f devclk 6-15: reserved 3-0 osfilt_soak r/w 0011 this field adjusts the iir soak time for the offset filtering feature. this field applies when offset filtering and background calibration are both enabled. this field determines how long the iir filter is allowed to settle when first connected to an adc after the adc is calibrated. after the soak time completes, the adc is placed online using the iir filter. set osfilt_soak = osfilt_bw. advance information
96 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.6 adc bank registers (0x100 to 0x15f) table 97. adc bank registers address reset acronym register name section 0x100-0x101 undefined reserved reserved ? 0x102 undefined b0_time_0 timing adjustment for bank 0 (0 clock) register timing adjustment for bank 0 (0 clock) register (address = 0x102) [reset = undefined] 0x103 undefined b0_time_90 timing adjustment for bank 0 ( ? 90 clock) register timing adjustment for bank 0 ( ? 90 clock) register (address = 0x103) [reset = undefined] 0x104-0x111 undefined reserved reserved ? 0x112 undefined b1_time_0 timing adjustment for bank 1 (0 clock) register timing adjustment for bank 1 (0 clock) register (address = 0x112) [reset = undefined] 0x113 undefined b1_time_90 timing adjustment for bank 1 ( ? 90 clock) register timing adjustment for bank 1 ( ? 90 clock) register (address = 0x113) [reset = undefined] 0x114-0x121 undefined reserved reserved ? 0x122 undefined b2_time_0 timing adjustment for bank 2 (0 clock) register timing adjustment for bank 2 (0 clock) register (address = 0x122) [reset = undefined] 0x123 undefined b2_time_90 timing adjustment for bank 2 ( ? 90 clock) register timing adjustment for bank 2 ( ? 90 clock) register (address = 0x123) [reset = undefined] 0x124-0x131 undefined reserved reserved ? 0x132 undefined b3_time_0 timing adjustment for bank 3 (0 clock) register timing adjustment for bank 3 (0 clock) register (address = 0x132) [reset = undefined] 0x133 undefined b3_time_90 timing adjustment for bank 3 ( ? 90 clock) register timing adjustment for bank 3 ( ? 90 clock) register (address = 0x133) [reset = undefined] 0x134-0x141 undefined reserved reserved ? 0x142 undefined b4_time_0 timing adjustment for bank 4 (0 clock) register timing adjustment for bank 4 (0 clock) register (address = 0x142) [reset = undefined] 0x143 undefined b4_time_90 timing adjustment for bank 4 ( ? 90 clock) register timing adjustment for bank 4 ( ? 90 clock) register (address = 0x143) [reset = undefined] 0x144-0x151 undefined reserved reserved ? 0x152 undefined b5_time_0 timing adjustment for bank 5 (0 clock) register timing adjustment for bank 5 (0 clock) register (address = 0x152) [reset = undefined] 0x153 undefined b5_time_90 timing adjustment for bank 5 ( ? 90 clock) register timing adjustment for bank 5 ( ? 90 clock) register (address = 0x153) [reset = undefined] 0x154-0x15f undefined reserved reserved ? 7.6.1.6.1 timing adjustment for bank 0 (0 clock) register (address = 0x102) [reset = undefined] figure 75. timing adjustment for bank 0 (0 clock) register (b0_time_0) 7 6 5 4 3 2 1 0 b0_time_0 r/w table 98. b0_time_0 field descriptions bit field type reset description 7-0 b0_time_0 r/w undefined time adjustment for bank 0 (applied when the adc is configured for 0 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. advance information
97 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.6.2 timing adjustment for bank 0 ( ? 90 clock) register (address = 0x103) [reset = undefined] figure 76. timing adjustment for bank 0 ( ? 90 clock) register (b0_time_90) 7 6 5 4 3 2 1 0 b0_time_90 r/w table 99. b0_time_90 field descriptions bit field type reset description 7-0 b0_time_90 r/w undefined time adjustment for bank 0 (applied when the adc is configured for ? 90 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.3 timing adjustment for bank 1 (0 clock) register (address = 0x112) [reset = undefined] figure 77. timing adjustment for bank 1 (0 clock) register (b1_time_0) 7 6 5 4 3 2 1 0 b1_time_0 r/w table 100. b1_time_0 field descriptions bit field type reset description 7-0 b1_time_0 r/w undefined time adjustment for bank 1 (applied when the adc is configured for 0 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.4 timing adjustment for bank 1 ( ? 90 clock) register (address = 0x113) [reset = undefined] figure 78. timing adjustment for bank 1 ( ? 90 clock) register (b1_time_90) 7 6 5 4 3 2 1 0 b1_time_90 r/w table 101. b1_time_90 field descriptions bit field type reset description 7-0 b1_time_90 r/w undefined time adjustment for bank 1 (applied when the adc is configured for ? 90 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.5 timing adjustment for bank 2 (0 clock) register (address = 0x122) [reset = undefined] figure 79. timing adjustment for bank 2 (0 clock) register (b2_time_0) 7 6 5 4 3 2 1 0 b2_time_0 r/w table 102. b2_time_0 field descriptions bit field type reset description 7-0 b2_time_0 r/w undefined time adjustment for bank 2 (applied when the adc is configured for 0 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. advance information
98 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.6.6 timing adjustment for bank 2 ( ? 90 clock) register (address = 0x123) [reset = undefined] figure 80. timing adjustment for bank 2 ( ? 90 clock) register (b2_time_90) 7 6 5 4 3 2 1 0 b2_time_90 r/w table 103. b2_time_90 field descriptions bit field type reset description 7-0 b2_time_90 r/w undefined time adjustment for bank 2 (applied when the adc is configured for ? 90 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.7 timing adjustment for bank 3 (0 clock) register (address = 0x132) [reset = undefined] figure 81. timing adjustment for bank 3 (0 clock) register (b3_time_0) 7 6 5 4 3 2 1 0 b3_time_0 r/w table 104. b3_time_0 field descriptions bit field type reset description 7-0 b3_time_0 r/w undefined time adjustment for bank 3 (applied when the adc is configured for 0 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.8 timing adjustment for bank 3 ( ? 90 clock) register (address = 0x133) [reset = undefined] figure 82. timing adjustment for bank 3 ( ? 90 clock) register (b3_time_90) 7 6 5 4 3 2 1 0 b3_time_90 r/w table 105. b3_time_90 field descriptions bit field type reset description 7-0 b3_time_90 r/w undefined time adjustment for bank 3 (applied when the adc is configured for ? 90 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.9 timing adjustment for bank 4 (0 clock) register (address = 0x142) [reset = undefined] figure 83. timing adjustment for bank 4 (0 clock) register (b4_time_0) 7 6 5 4 3 2 1 0 b4_time_0 r/w table 106. b4_time_0 field descriptions bit field type reset description 7-0 b4_time_0 r/w undefined time adjustment for bank 4 (applied when the adc is configured for 0 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. advance information
99 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.6.10 timing adjustment for bank 4 ( ? 90 clock) register (address = 0x143) [reset = undefined] figure 84. timing adjustment for bank 4 ( ? 90 clock) register (b4_time_90) 7 6 5 4 3 2 1 0 b4_time_90 r/w table 107. b4_time_90 field descriptions bit field type reset description 7-0 b4_time_90 r/w undefined time adjustment for bank 4 (applied when the adc is configured for ? 90 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.11 timing adjustment for bank 5 (0 clock) register (address = 0x152) [reset = undefined] figure 85. timing adjustment for bank 5 (0 clock) register (b5_time_0) 7 6 5 4 3 2 1 0 b5_time_0 r/w table 108. b5_time_0 field descriptions bit field type reset description 7-0 b5_time_0 r/w undefined time adjustment for bank 5 (applied when the adc is configured for 0 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. 7.6.1.6.12 timing adjustment for bank 5 ( ? 90 clock) register (address = 0x153) [reset = undefined] figure 86. timing adjustment for bank 5 ( ? 90 clock) register (b5_time_90) 7 6 5 4 3 2 1 0 b5_time_90 r/w table 109. b5_time_90 field descriptions bit field type reset description 7-0 b5_time_90 r/w undefined time adjustment for bank 5 (applied when the adc is configured for ? 90 clock phase). after reset, the factory-trimmed value can be read and adjusted as required. advance information
100 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.7 lsb control registers (0x160 to 0x1ff) table 110. lsb control registers address reset acronym register name section 0x160 0x00 enc_lsb lsb control bit output register figure 87 0x161-0x1ff undefined reserved reserved ? 7.6.1.7.1 lsb control bit output register (address = 0x160) [reset = 0x00] figure 87. lsb control bit output register (enc_lsb) 7 6 5 4 3 2 1 0 reserved timestamp_en r/w-0000 000 r/w-0 table 111. enc_lsb field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 timestamp_en r/w 0 when set, the transport layer transmits the timestamp signal on the lsb of the output samples. only supported in decimate-by-1 (ddc bypass) modes. timestamp_en has priority over cal_state_en. tmstp_recv_en must also be set high when using timestamp. the latency of the timestamp signal (through the entire device) matches the latency of the analog adc inputs. in 8-bit modes, the control bit is placed on the lsb of the 8-bit samples (leaving 7 bits of sample data). if the device is configured for 12-bit data, the control bit is placed on the lsb of the 12-bit data (leaving 11 bits of sample data). the control bit enabled by this register is never advertised in the ila (the cs field is 0 in the ila). advance information
101 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.8 jesd204b registers (0x200 to 0x20f) table 112. jesd204b registers address reset acronym register name section 0x200 0x01 jesd_en jesd204b enable register jesd204b enable register (address = 0x200) [reset = 0x01] 0x201 0x02 jmode jesd204b mode register jesd204b mode register (address = 0x201) [reset = 0x02] 0x202 0x1f km1 jesd204b k parameter register jesd204b k parameter register (address = 0x202) [reset = 0x1f] 0x203 0x01 jsync_n jesd204b manual sync request register jesd204b manual sync request register (address = 0x203) [reset = 0x01] 0x204 0x02 jctrl jesd204b control register jesd204b control register (address = 0x204) [reset = 0x02] 0x205 0x00 jtest jesd204b test pattern control register jesd204b test pattern control register (address = 0x205) [reset = 0x00] 0x206 0x00 did jesd204b did parameter register jesd204b did parameter register (address = 0x206) [reset = 0x00] 0x207 0x00 fchar jesd204b frame character register jesd204b frame character register (address = 0x207) [reset = 0x00] 0x208 undefined jesd_status jesd204b, system status register jesd204b, system status register (address = 0x208) [reset = undefined] 0x209 0x00 pd_ch jesd204b channel power-down jesd204b channel power-down register (address = 0x209) [reset = 0x00] 0x20a 0x00 jextra_a jesd204b extra lane enable (link a) jesd204b extra lane enable (link a) register (address = 0x20a) [reset = 0x00] 0x20b 0x00 jextra_b jesd204b extra lane enable (link b) jesd204b extra lane enable (link b) register (address = 0x20b) [reset = 0x00] 0x20c-0x20f undefined reserved reserved ? 7.6.1.8.1 jesd204b enable register (address = 0x200) [reset = 0x01] figure 88. jesd204b enable register (jesd_en) 7 6 5 4 3 2 1 0 reserved jesd_en r/w-0000 000 r/w-1 table 113. jesd_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 jesd_en r/w 1 0 : disables jesd204b interface 1 : enables jesd204b interface before altering other jesd204b registers, jesd_en must be cleared. when jesd_en is 0, the block is held in reset and the serializers are powered down. the clocks are gated off to save power. the lmfc counter is also held in reset, so sysref does not align the lmfc. always set cal_en before setting jesd_en. always clear jesd_en before clearing cal_en. advance information
102 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.8.2 jesd204b mode register (address = 0x201) [reset = 0x02] figure 89. jesd204b mode register (jmode) 7 6 5 4 3 2 1 0 reserved jmode r/w-000 r/w-0001 0 table 114. jmode field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4-0 jmode r/w 0001 0 specify the jesd204b output mode (including ddc decimation factor). only change this register when jesd_en = 0 and cal_en = 0. 7.6.1.8.3 jesd204b k parameter register (address = 0x202) [reset = 0x1f] figure 90. jesd204b k parameter register (km1) 7 6 5 4 3 2 1 0 reserved km1 r/w-000 r/w-1111 1 table 115. km1 field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4-0 km1 r/w 1111 1 k is the number of frames per multiframe and this register must be programmed as k-1. depending on the jmode setting, there are constraints on the legal values of k. (default: km1 = 31, k = 32). only change this register when jesd_en is 0. 7.6.1.8.4 jesd204b manual sync request register (address = 0x203) [reset = 0x01] figure 91. jesd204b manual sync request register (jsync_n) 7 6 5 4 3 2 1 0 reserved jsync_n r/w-0000 000 r/w-1 table 116. jsync_n field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 jsync_n r/w 1 set this bit to 0 to request jesd204b synchronization (equivalent to the syncse pin being asserted). for normal operation, leave this bit set to 1. the jsync_n register can always generate a synchronization request, regardless of the sync_sel register. however, if the selected sync pin is stuck low, the synchronization request cannot be de-asserted unless sync_sel = 2 is programmed. advance information
103 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.8.5 jesd204b control register (address = 0x204) [reset = 0x02] figure 92. jesd204b control register (jctrl) 7 6 5 4 3 2 1 0 reserved sync_sel sformat scr r/w-0000 r/w-00 r/w-1 r/w-0 table 117. jctrl field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-2 sync_sel r/w 00 0: use the syncse input for the sync~ function (default) 1: use the tmstp differential input for the sync~ function; tmstp_recv_en must also be set 2: do not use any sync input signal (use software sync~ through jsync_n) 1 sformat r/w 1 output sample format for jesd204b samples. 0: offset binary 1: signed 2 ? s complement (default) 0 scr r/w 0 0: scrambler disabled (default) 1: scrambler enabled only change this register when jesd_en is 0. 7.6.1.8.6 jesd204b test pattern control register (address = 0x205) [reset = 0x00] figure 93. jesd204b test pattern control register (jtest) 7 6 5 4 3 2 1 0 reserved jtest r/w-0000 r/w-0000 table 118. jtest field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-0 jtest r/w 0000 0: test mode disabled; normal operation (default) 1: prbs7 test mode 2: prbs15 test mode 3: prbs23 test mode 4: ramp test mode 5: transport layer test mode 6: d21.5 test mode 7: k28.5 test mode 8: repeated ila test mode 9: modified rpat test mode 10: serial outputs held low 11: serial outputs held high 12 ? 15: reserved only change this register when jesd_en is 0. advance information
104 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.8.7 jesd204b did parameter register (address = 0x206) [reset = 0x00] figure 94. jesd204b did parameter register (did) 7 6 5 4 3 2 1 0 did r/w-0000 0000 table 119. did field descriptions bit field type reset description 7-0 did r/w 0000 0000 specifies the device id (did) value that is transmitted during the second multiframe of the jesd204b ila. link a transmits did, and link b transmits did+1. bit 0 is ignored and always returns 0 (if an odd number is programmed, that number is decremented to an even number). only change this register when jesd_en is 0. 7.6.1.8.8 jesd204b frame character register (address = 0x207) [reset = 0x00] figure 95. jesd204b frame character register (fchar) 7 6 5 4 3 2 1 0 reserved fchar r/w-0000 00 r/w-00 table 120. fchar field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1-0 fchar r/w 00 specify which comma character is used to denote end-of-frame. this character is transmitted opportunistically (see the frame and multiframe monitoring section). 0: use k28.7 (default, jesd204b compliant) 1: use k28.1 (not jesd204b compliant) 2: use k28.5 (not jesd204b compliant) 3: reserved when using a jesd204b receiver, always use fchar = 0. when using a general-purpose 8b, 10b receiver, the k28.7 character may cause issues. when k28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers realign to the false comma. to avoid this condition, program fchar to 1 or 2. only change this register when jesd_en is 0. 7.6.1.8.9 jesd204b, system status register (address = 0x208) [reset = undefined] figure 96. jesd204b, system status register (jesd_status) 7 6 5 4 3 2 1 0 reserved link_up sync_status realigned aligned pll_locked reserved r r r r/w r/w r r table 121. jesd_status field descriptions bit field type reset description 7 reserved r undefined reserved 6 link_up r undefined when set, this bit indicates that the jesd204b link is up. 5 sync_status r undefined returns the state of the jesd204b sync~ signal. 0: sync~ asserted 1: sync~ de-asserted advance information
105 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 121. jesd_status field descriptions (continued) bit field type reset description 4 realigned r/w undefined when high, this bit indicates that an internal digital clock, frame clock, or multiframe (lmfc) clock phase was realigned by sysref. write a 1 to clear this bit. 3 aligned r/w undefined when high, this bit indicates that the multiframe (lmfc) clock phase has been established by sysref. the first sysref event after enabling the jesd204b encoder will set this bit. write a 1 to clear this bit. 2 pll_locked r undefined when high, this bit indicates that the pll is locked. 1-0 reserved r undefined reserved 7.6.1.8.10 jesd204b channel power-down register (address = 0x209) [reset = 0x00] figure 97. jesd204b channel power-down register (pd_ch) 7 6 5 4 3 2 1 0 reserved pd_bch pd_ach r/w-0000 00 r/w-0 r/w-0 table 122. pd_ch field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 pd_bch r/w 0 when set, the b adc channel is powered down. the digital channels that are bound to the b adc channel are also powered down (see the digital channel binding register ). important notes: set jesd_en = 0 before changing pd_ch. to power-down both adc channels, use mode. if both channels are powered down, then the entire jesd204b subsystem (including the pll and lmfc) are powered down if the selected jesd204b mode transmits a and b data on link a, and the b digital channel is disabled, link a remains operational, but the b-channel samples are undefined. 0 pd_ach r/w 0 when set, the a adc channel is powered down. the digital channels that are bound to the a adc channel are also powered down ( digital channel binding register ). important notes: set jesd_en = 0 before changing pd_ch. to power-down both adc channels, use mode. if both channels are powered down, then the entire jesd204b subsystem (including the pll and lmfc) are powered down if the selected jesd204b mode transmits a and b data on link a, and the b digital channel is disabled, link a remains operational, but the b-channel samples are undefined. advance information
106 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.8.11 jesd204b extra lane enable (link a) register (address = 0x20a) [reset = 0x00] figure 98. jesd204b extra lane enable (link a) register (jextra_a) 7 6 5 4 3 2 1 0 extra_lane_a extra_ser_a r/w-0000 000 r/w-0 table 123. jesd204b extra lane enable (link a) field descriptions bit field type reset description 7-1 extra_lane_a r/w 0000 000 program these register bits to enable extra lanes (even if the selected jmode does not require the lanes to be enabled). extra_lane_a(n) enables an (n = 1 to 7). this register enables the link layer clocks for the affected lanes. to also enable the extra serializes set extra_ser_a = 1. 0 extra_ser_a r/w 0 0: only the link layer clocks for extra lanes are enabled. 1: serializers for extra lanes are also enabled. use this mode to transmit data from the extra lanes. important notes: only change this register when jesd_en = 0. the bit-rate and mode of the extra lanes are set by the jmode and jtest parameters. this register does not override the pd_ch register, so ensure that the link is enabled to use this feature. to enable serializer n, the lower number lanes 0 to n-1 must also be enabled, otherwise serializer n does not receive a clock. 7.6.1.8.12 jesd204b extra lane enable (link b) register (address = 0x20b) [reset = 0x00] figure 99. jesd204b extra lane enable (link b) register (jextra_b) 7 6 5 4 3 2 1 0 extra_lane_b extra_ser_b r/w-0000 000 r/w-0 table 124. jesd204b extra lane enable (link b) field descriptions bit field type reset description 7-1 extra_lane_b r/w 0000 000 program these register bits to enable extra lanes (even if the selected jmode does not require the lanes to be enabled). extra_lane_b(n) enables bn (n = 1 to 7). this register enables the link layer clocks for the affected lanes. to also enable the extra serializes set extra_ser_b = 1. 0 extra_ser_b r/w 0 0: only the link layer clocks for extra lanes are enabled. 1: serializers for extra lanes are also enabled. use this mode to transmit data from the extra lanes. important notes: only change this register when jesd_en = 0. the bit-rate and mode of the extra lanes are set by the jmode and jtest parameters. this register does not override the pd_ch register, so ensure that the link is enabled to use this feature. to enable serializer n, the lower number lanes 0 to n-1 must also be enabled, otherwise serializer n does not receive a clock. advance information
107 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9 digital down converter registers (0x210-0x2af) table 125. digital down converter and overrange registers address reset acronym register name section 0x210 0x00 ddc_cfg ddc configuration register ddc configuration register (address = 0x210) [reset = 0x00] 0x211 0xf2 ovr_t0 overrange threshold 0 register overrange threshold 0 register (address = 0x211) [reset = 0xf2] 0x212 0xab ovr_t1 overrange threshold 1 register overrange threshold 1 register (address = 0x212) [reset = 0xab] 0x213 0x07 ovr_cfg overrange configuration register overrange configuration register (address = 0x213) [reset = 0x07] 0x214 0x00 cmode ddc configuration preset mode register ddc configuration preset mode register (address = 0x214) [reset = 0x00] 0x215 0x00 csel ddc configuration preset select register ddc configuration preset select register (address = 0x215) [reset = 0x00] 0x216 0x02 dig_bind digital channel binding register digital channel binding register (address = 0x216) [reset = 0x02] 0x217-0x218 0x0000 nco_rdiv rational nco reference divisor register rational nco reference divisor register (address = 0x217 to 0x218) [reset = 0x0000] 0x219 0x02 nco_sync nco synchronization register nco synchronization register (address = 0x219) [reset = 0x02] 0x21a-0x21f undefined reserved reserved ? 0x220-0x223 0xc0000000 freqa0 nco frequency (ddc a preset 0) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x224-0x225 0x0000 phasea0 nco phase (ddc a preset 0) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x226-0x227 undefined reserved reserved ? 0x228-0x22b 0xc0000000 freqa1 nco frequency (ddc a preset 1) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x22c-0x22d 0x0000 phasea1 nco phase (ddc a preset 1) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x22e-0x22f undefined reserved reserved ? 0x230-0x233 0xc0000000 freqa2 nco frequency (ddc a preset 2) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x234-0x235 0x0000 phasea2 nco phase (ddc a preset 2) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x236-0x237 undefined reserved reserved ? 0x238-0x23b 0xc0000000 freqa3 nco frequency (ddc a preset 3) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x23c-0x23d 0x0000 phasea3 nco phase (ddc a preset 3) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x23e-0x23f undefined reserved reserved ? 0x240-0x243 0xc0000000 freqb0 nco frequency (ddc b preset 0) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x244-0x245 0x0000 phaseb0 nco phase (ddc b preset 0) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x246-0x247 undefined reserved reserved ? 0x248-0x24b 0xc0000000 freqb1 nco frequency (ddc b preset 1) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x24c-0x24d 0x0000 phaseb1 nco phase (ddc b preset 1) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x24e-0x24f undefined reserved reserved ? 0x250-0x253 0xc0000000 freqb2 nco frequency (ddc b preset 2) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x254-0x255 0x0000 phaseb2 nco phase (ddc b preset 2) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x256-0x257 undefined reserved reserved ? 0x258-0x25b 0xc0000000 freqb3 nco frequency (ddc b preset 3) nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] 0x25c-0x25d 0x0000 phaseb3 nco phase (ddc b preset 3) nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] advance information
108 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated table 125. digital down converter and overrange registers (continued) address reset acronym register name section 0x25e-0x296 undefined reserved reserved ? 0x297 undefined spin_id spin identification value spin identification register (address = 0x297) [reset = undefined] 0x298-0x2af undefined reserved reserved ? 7.6.1.9.1 ddc configuration register (address = 0x210) [reset = 0x00] figure 100. ddc configuration register (ddc_cfg) 7 6 5 4 3 2 1 0 reserved d4_ap87 d2_high_pass invert_spectrum boost r/w-0000 r/w-0 r/w-0 r/w-0 r/w-0 table 126. ddc_cfg field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3 d4_ap87 r/w 0 0: decimate-by-4 mode uses 80% alias protection, > 80-db suppression 1: decimate-by-4 mode uses 87.5% alias protection, > 60-db suppression 2 d2_high_pass r/w 0 0: decimate-by-2 mode uses a low-pass filter 1: decimate-by-2 mode uses a high-pass filter. decimating the high-pass signal causes spectral inversion. this inversion can be undone by setting invert_spectrum. 1 invert_spectrum r/w 0 0: no inversion applied to output spectrum 1: output spectrum is inverted this register only applies when the ddc is enabled and is producing a real output (not complex). the spectrum is inverted by mixing the signal with fsout / 2 (for example, invert all odd samples). 0 boost r/w 0 ddc gain control. only applies to ddc modes with complex decimation. 0: final filter has 0-db gain (default) 1: final filter has 6.02-db gain. only use this setting when certain that the negative image of the input signal is filtered out by the ddc, otherwise digital clipping may occur. 7.6.1.9.2 overrange threshold 0 register (address = 0x211) [reset = 0xf2] figure 101. overrange threshold 0 register (ovr_t0) 7 6 5 4 3 2 1 0 ovr_t0 r/w-1111 0010 table 127. ovr_t0 field descriptions bit field type reset description 7-0 ovr_t0 r/w 1111 0010 overrange threshold 0. this parameter defines the absolute sample level that causes control bit 0 to be set. the detection level in dbfs (peak) is: 20 log10 (ovr_t0 / 256) default: 0xf2 = 242 ? 0.5 dbfs. advance information
109 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9.3 overrange threshold 1 register (address = 0x212) [reset = 0xab] figure 102. overrange threshold 1 register (ovr_t1) 7 6 5 4 3 2 1 0 ovr_t1 r/w-1010 1011 table 128. ovr_t1 field descriptions bit field type reset description 7-0 ovr_t1 r/w 1010 1011 overrange threshold 1. this parameter defines the absolute sample level that causes control bit 1 to be set. the detection level in dbfs (peak) is: 20 log10 (ovr_t1 / 256) default: 0xab = 171 ? 3.5 dbfs. 7.6.1.9.4 overrange configuration register (address = 0x213) [reset = 0x07] figure 103. overrange configuration register (ovr_cfg) 7 6 5 4 3 2 1 0 reserved ovr_en ovr_n r/w-0000 r/w-0 r/w-111 (1) changing the ovr_n setting while jesd_en=1 may cause the phase of the monitoring period to change. table 129. ovr_cfg field descriptions bit field type reset description 7-4 reserved r/w 0000 0 reserved 3 ovr_en r/w 0 enables overrange status output pins when set high. the ora0, ora1, orb0, and orb1 outputs are held low when ovr_en is set low. this register only effects the overrange output pins (orxx) and not the overrange status embedded in the data samples. 2-0 ovr_n (1) r/w 111 program this register to adjust the pulse extension for the ora0, ora1 and orb0, orb1 outputs. the minimum pulse duration of the overrange outputs is 8 2 ovr_n devclk cycles. incrementing this field doubles the monitoring period. advance information
110 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9.5 ddc configuration preset mode register (address = 0x214) [reset = 0x00] figure 104. ddc configuration preset mode register (cmode) 7 6 5 4 3 2 1 0 reserved cmode r/w-0000 00 r/w-00 table 130. cmode field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1-0 cmode r/w 00 the nco frequency and phase for ddc a are set by the freqax and phaseax registers and the nco frequency and phase for ddc b are set by the freqbx and phasebx registers, where x is the configuration preset (0 through 3). 0: use csel register to select the active nco configuration preset for ddc a and ddc b 1: use ncoa[1:0] pins to select the active nco configuration preset for ddc a and use ncob[1:0] pins to select the active nco configuration preset for ddc b 2: use ncoa[1:0] pins to select the active nco configuration preset for both ddc a and ddc b 3: reserved 7.6.1.9.6 ddc configuration preset select register (address = 0x215) [reset = 0x00] figure 105. ddc configuration preset select register (csel) 7 6 5 4 3 2 1 0 reserved cselb csela r/w-0000 r/w-00 r/w-00 table 131. csel field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-2 cselb r/w 00 when cmode = 0, this register is used to select the active nco configuration preset for ddc b. 1-0 csela r/w 00 when cmode = 0, this register is used to select the active nco configuration preset for ddc a. example: if csela = 0, then freqa0 and phasea0 are the active settings. if csela = 1, then freqa1 and phasea1 are the active settings. advance information
111 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9.7 digital channel binding register (address = 0x216) [reset = 0x02] figure 106. digital channel binding register (dig_bind) 7 6 5 4 3 2 1 0 reserved dig_bind_b dig_bind_a r/w-0000 00 r/w-1 r/w-0 table 132. dig_bind field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 dig_bind_b r/w 0 digital channel b input select: 0: digital channel b receives data from adc channel a 1: digital channel b receives data from adc channel b (default) 0 dig_bind_a r/w 0 digital channel a input select: 0: digital channel a receives data from adc channel a (default) 1: digital channel a receives data from adc channel b when using single-channel mode, always use the default setting for dig_bind or the device does not work. set jesd_en = 0 and cal_en = 0 before changing dig_bind. the dig_bind setting is combined with pd_ach, pd_bch to determine if a digital channel is powered down. each digital channel (and link) is powered down when the adc channel it is bound to is powered down (by pd_ach, pd_bch). 7.6.1.9.8 rational nco reference divisor register (address = 0x217 to 0x218) [reset = 0x0000] figure 107. rational nco reference divisor register (nco_rdiv) 15 14 13 12 11 10 9 8 nco_rdiv[15:8] r/w-0000 0000 7 6 5 4 3 2 1 0 nco_rdiv[7:0] r/w-0000 0000 table 133. nco_rdiv field descriptions bit field type reset description 15-0 nco_rdiv r/w 0x0000h sometimes the 32-bit nco frequency word does not provide the desired frequency step size and can only approximate the desired frequency. this condition results in a frequency error. use this register to eliminate the frequency error. this register is used for all configuration presets; see the rational nco frequency setting mode section. advance information
112 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9.9 nco synchronization register (address = 0x219) [reset = 0x02] figure 108. nco synchronization register (nco_sync) 7 6 5 4 3 2 1 0 reserved nco_sync_ila nco_sync_next r/w-0000 00 r/w-1 r/w-0 table 134. nco_sync field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 nco_sync_ila r/w 0 when this bit is set, the nco phase is initialized by the lmfc edge that starts the ila sequence (default). 0 nco_sync_next r/w 0 after writing a 0 and then a 1 to this bit, the next sysref rising edge initializes the nco phase. when the nco phase is initialized by sysref, the nco does not reinitialize on future sysref edges unless a 0 and a 1 is written to this bit again. follow these steps to align the nco in multiple parts: ? ensure the device is powered up, jesd_en is set, and the device clock is running. ? ensure that sysref is disabled (not toggling). ? program nco_sync_ila = 0 on all devices. ? write nco_sync_next = 0 on all devices. ? write nco_sync_next = 1 on all devices. nco sync is armed. ? instruct the sysref source to generate 1 or more sysref pulses. ? all devices initialize their nco using the first sysref rising edge. 7.6.1.9.10 nco frequency (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] figure 109. nco frequency (ddc a or ddc b and preset x) register (freqax or freqbx) 31 30 29 28 27 26 25 24 freqax[31:24] or freqbx[31:24] r/w-0xc0 23 22 21 20 19 18 17 16 freqax[23:16] or freqbx[23:16] r/w-0x00 15 14 13 12 11 10 9 8 freqax[15:8] or freqbx[15:8] r/w-0x00 7 6 5 4 3 2 1 0 freqax[7:0] or freqbx[7:0] r/w-0x00 table 135. freqax or freqbx field descriptions bit field type reset description 31-0 freqax or freqbx r/w see table 125 changing this register after the jesd204b interface is running results in non-deterministic nco phase. if deterministic phase is required, the jesd204b interface must be re-initialized after changing this register. this register can be interpreted as signed or unsigned. when interpreted as signed (2's complement) the nco frequency is between ? f s / 2 to f s / 2. when interpreted as unsigned the nco frequency is between 0 and f s . advance information
113 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9.11 nco phase (ddc a or ddc b and preset x) register (address = see table 125 ) [reset = see table 125 ] figure 110. nco phase (ddc a or ddc b and preset x) register (phaseax or phasebx) 15 14 13 12 11 10 9 8 phaseax[15:8] or phasebx[15:8] r/w-0x00 7 6 5 4 3 2 1 0 phaseax[7:0] or phasebx[7:0] r/w-0x00 table 136. phaseax or phasebx field descriptions bit field type reset description 15-0 phaseax or phasebx r/w see table 125 this value is msb-justified into a 32-bit field and then added to the phase accumulator. this register can be interpreted as signed or unsigned; see the nco phase offset setting section. 7.6.1.10 spin identification register (address = 0x297) [reset = undefined] figure 111. spin identification register (spin_id) 7 6 5 4 3 2 1 0 reserved spin_id r-000 r table 137. spin_id field descriptions bit field type reset description 7-5 reserved r 000 reserved 4-0 spin_id r 5 spin identification value. 5 : ADC12DJ3200QML-SP advance information
114 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.2 sysref calibration registers (0x2b0 to 0x2bf) table 138. sysref calibration registers address reset acronym register name section 0x2b0 0x00 src_en sysref calibration enable register sysref calibration enable register (address = 0x2b0) [reset = 0x00] 0x2b1 0x05 src_cfg sysref calibration configuration register sysref calibration configuration register (address = 0x2b1) [reset = 0x05] 0x2b2-0x2b4 undefined src_status sysref calibration status sysref calibration status register (address = 0x2b2 to 0x2b4) [reset = undefined] 0x2b5-0x2b7 0x00 tad devclk aperture delay adjustment register devclk aperture delay adjustment register (address = 0x2b5 to 0x2b7) [reset = 0x000000] 0x2b8 0x00 tad_ramp devclk timing adjust ramp control register devclk timing adjust ramp control register (address = 0x2b8) [reset = 0x00] 0x2b9-0x2bf undefined reserved reserved ? 7.6.2.1 sysref calibration enable register (address = 0x2b0) [reset = 0x00] figure 112. sysref calibration enable register (src_en) 7 6 5 4 3 2 1 0 reserved src_en r/w-0000 000 r/w-0 table 139. src_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 src_en r/w 0 0: sysref calibration disabled; use the tad register to manually control the tad[16:0] output and adjust the devclk delay (default) 1: sysref calibration enabled; the devclk delay is automatically calibrated; the tad register is ignored a 0-to-1 transition on src_en starts the sysref calibration sequence. program src_cfg before setting src_en. ensure that adc calibration is not currently running before setting src_en. advance information
115 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.2.2 sysref calibration configuration register (address = 0x2b1) [reset = 0x05] figure 113. sysref calibration configuration register (src_cfg) 7 6 5 4 3 2 1 0 reserved src_avg src_hdur r/w-0000 r/w-01 r/w-01 table 140. src_cfg field descriptions bit field type reset description 7-4 reserved r/w 0000 00 reserved 3-2 src_avg r/w 01 specifies the amount of averaging used for sysref calibration. larger values increase calibration time and reduce the variance of the calibrated value. 0: 4 averages 1: 16 averages 2: 64 averages 3: 256 averages 1-0 src_hdur r/w 01 specifies the duration of each high-speed accumulation for sysref calibration. if the sysref period exceeds the supported value, the calibration fails. larger values increase calibration time and support longer sysref periods. for a given sysref period, larger values also reduce the variance of the calibrated value. 0: 4 cycles per accumulation, max sysref period of 85 devclk cycles 1: 16 cycles per accumulation, max sysref period of 1100 devclk cycles 2: 64 cycles per accumulation, max sysref period of 5200 devclk cycles 3: 256 cycles per accumulation, max sysref period of 21580 devclk cycles max duration of sysref calibration is bounded by: t sysrefcal (in devclk cycles) = 256 19 4 (src_avg + src_hdur + 2) 7.6.2.3 sysref calibration status register (address = 0x2b2 to 0x2b4) [reset = undefined] figure 114. sysref calibration status register (src_status) 23 22 21 20 19 18 17 16 reserved src_done src_tad[16] r r r 15 14 13 12 11 10 9 8 src_tad[15:8] r 7 6 5 4 3 2 1 0 src_tad[7:0] r table 141. src_status field descriptions bit field type reset description 23-18 reserved r undefined reserved 17 src_done r undefined this bit returns a 1 when src_en = 1 and sysref calibration is complete. 16-0 src_tad r undefined this field returns the value for tad[16:0] computed by the sysref calibration. this field is only valid if src_done = 1. advance information
116 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.2.4 devclk aperture delay adjustment register (address = 0x2b5 to 0x2b7) [reset = 0x000000] figure 115. devclk aperture delay adjustment register (tad) 23 22 21 20 19 18 17 16 reserved tad_inv r/w-0000 000 r/w-0 15 14 13 12 11 10 9 8 tad_coarse r/w-0000 0000 7 6 5 4 3 2 1 0 tad_fine r/w-0000 0000 table 142. tad field descriptions bit field type reset description 23-17 reserved r/w 0000 000 reserved 16 tad_inv r/w 0 invert devclk by setting this bit equal to 1. 15-8 tad_coarse r/w 0000 0000 this register controls the devclk aperture delay adjustment when src_en = 0. use this register to manually control the devclk aperture delay when sysref calibration is disabled. if adc calibration or jesd204b is running, ti recommends gradually increasing or decreasing this value (1 code at a time) to avoid clock glitches. see the switching characteristics table for tad_coarse resolution. 7-0 tad_fine r/w 0000 0000 see the switching characteristics table for tad_fine resolution. 7.6.2.5 devclk timing adjust ramp control register (address = 0x2b8) [reset = 0x00] figure 116. devclk timing adjust ramp control register (tad_ramp) 7 6 5 4 3 2 1 0 reserved tad_ramp_rate tad_ramp_en r/w-0000 00 r/w-0 r/w-0 table 143. tad_ramp field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 tad_ramp_rate r/w 0 specifies the ramp rate for the tad[15:8] output when the tad[15:8] register is written when tad_ramp_en = 1. 0: tad[15:8] ramps up or down one code per 256 devclk cycles. 1: tad[15:8] ramps up or down 4 codes per 256 devclk cycles. 0 tad_ramp_en r/w 0 tad ramp enable. set this bit if coarse tad adjustments are desired to ramp up or down instead of changing abruptly. 0: after writing the tad[15:8] register the aperture delay is updated within 1024 devclk cycles 1: after writing the tad[15:8] register the aperture delay ramps up or down until the aperture delay matches the tad[15:8] register advance information
117 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.3 alarm registers (0x2c0 to 0x2c2) table 144. alarm registers address reset acronym register name section 0x2c0 undefined alarm alarm interrupt status register alarm interrupt register (address = 0x2c0) [reset = undefined] 0x2c1 0x1f alm_status alarm status register alarm status register (address = 0x2c1) [reset = 0x1f] 0x2c2 0x1f alm_mask alarm mask register alarm mask register (address = 0x2c2) [reset = 0x1f] 7.6.3.1 alarm interrupt register (address = 0x2c0) [reset = undefined] figure 117. alarm interrupt register (alarm) 7 6 5 4 3 2 1 0 reserved alarm r r table 145. alarm field descriptions bit field type reset description 7-1 reserved r undefined reserved 0 alarm r undefined this bit returns a 1 whenever any alarm occurs that is unmasked in the alm_status register. use alm_mask to mask (disable) individual alarms. cal_status_sel can be used to drive the alarm bit onto the calstat output pin to provide a hardware alarm interrupt signal. 7.6.3.2 alarm status register (address = 0x2c1) [reset = 0x1f] figure 118. alarm status register (alm_status) 7 6 5 4 3 2 1 0 reserved pll_alm link_alm realigned_alm nco_alm clk_alm r/w-000 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 table 146. alm_status field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4 pll_alm r/w 1 pll lock lost alarm. this bit is set whenever the pll is not locked. write a 1 to clear this bit. 3 link_alm r/w 1 link alarm. this bit is set whenever the jesd204b link is enabled, but is not in the data_enc state. write a 1 to clear this bit. 2 realigned_alm r/w 1 realigned alarm. this bit is set whenever sysref causes the internal clocks (including the lmfc) to be realigned. write a 1 to clear this bit. 1 nco_alm r/w 1 nco alarm. this bit can be used to detect an upset to the nco phase. this bit is set when any of the following occur: ? the ncos are disabled (jesd_en = 0) ? the ncos are synchronized (intentionally or unintentionally) ? any phase accumulators in channel a do not match channel b write a 1 to clear this bit. 0 clk_alm r/w 1 clock alarm. this bit can be used to detect an upset to the digital block and jesd204b clocks. this bit is set whenever the internal clock dividers for the a and b channels do not match. write a 1 to clear this bit. advance information
118 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.3.3 alarm mask register (address = 0x2c2) [reset = 0x1f] figure 119. alarm mask register (alm_mask) 7 6 5 4 3 2 1 0 reserved mask_pll_alm mask_link_alm mask_realigne d_alm mask_nco_alm mask_clk_alm r/w-000 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 table 147. alm_mask field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4 mask_pll_alm r/w 1 when set, pll_alm is masked and does not impact the alarm register bit. 3 mask_link_alm r/w 1 when set, link_alm is masked and does not impact the alarm register bit. 2 mask_realigned_alm r/w 1 when set, realigned_alm is masked and does not impact the alarm register bit. 1 mask_nco_alm r/w 1 when set, nco_alm is masked and does not impact the alarm register bit. 0 mask_clk_alm r/w 1 when set, clk_alm is masked and does not impact the alarm register bit. advance information
119 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated (1) see the third-party products disclaimer section. 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the ADC12DJ3200QML-SP can be used in a wide range of space-based applications including wideband satellite communications (satcom) and synthetic aperture radar (sar). the wide input bandwidth enables direct rf sampling to at least 8 ghz and the high sampling rate allows signal bandwidths of greater than 2 ghz. the typical application section describes one configuration that meets the needs of a number of these applications while the following sections describe generic application information. 8.1.1 analog inputs most applications can be narrowed down into two categories: those that need dc coupling and those that do not need dc coupling. the needs and interface recommendations for each category are different. in most cases, the driving circuit will need to perform a conversion from single-ended signaling at the signal source to differential signaling for the ADC12DJ3200QML-SP inputs. applications that require dc coupling will need to use a dc coupled amplifier to drive the adc. dc coupling is often more difficult due to the need for matched common-mode voltage (v cm ) between the driver amplifier and ADC12DJ3200QML-SP. ADC12DJ3200QML-SP makes this easy for many applications due to the 0-v input common-mode voltage (v icm ). a 0-v v icm allows a split supply differential amplifier to drive the adc directly with no v cm shift which in turn allows the amplifier to operate at its optimal operating point, typically with an output common-mode voltage (v ocm ) equal to the midpoint of the two supplies. if the differential amplifier has a pin to set its v ocm then that pin can be tied directly to gnd. an example amplifier that is capable of driving ADC12DJ3200QML-SP is the lmh5401-sp which is capable of converting from single-ended to differential signaling and a high gain-bandwidth product to match the ADC12DJ3200QML-SP bandwidth capabilties. the second category, applications that do not require dc coupling, will often find that best performance can be achieved using transformers or baluns to convert from single-ended to differential signaling. these transformers can also perform impedance conversion such that a 50- , single-ended source is well matched to the 100- , differential termination inside of the ADC12DJ3200QML-SP. for instance, a 1:2 impedance ratio transformer can provide both single-ended to differential conversion and proper impedance matching. the transformer outputs can be either ac-coupled, or directly connected to the adc differential inputs, which are terminated internally to gnd on each input pin through a 50- resistor. baluns must be selected to cover the needed frequency range, have a 1:2 impedance ratio, and have acceptable gain and phase balance over the frequency range of interest. poor gain and phase balance will result in degraded 2nd-harmonic distortion performance. table 148 lists a number of recommended baluns for different frequency ranges, but is not fully inclusive. table 148. recommended baluns part number manufacturer (1) minimum frequency (mhz) maximum frequency (mhz) bal-0009smg marki microwave 0.5 9000 bal-0208smg marki microwave 2000 8000 tcm2-43x+ mini-circuits 10 4000 tcm2-33wx+ mini-circuits 10 3000 b0430j50100ahf anaren 400 3000 advance information
120 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 8.1.2 analog input bandwidth ADC12DJ3200QML-SP has a very high full-power input bandwidth to allow direct sampling of signals up to 10 ghz. the analog inputs of ADC12DJ3200QML-SP are tuned for highest bandwidth when the signal source is a high-quality (good return loss) 100- differential source. a 2:1 transformer will present a 100- differential source impedance to the adc from a single-ended 50- source. additional impedance matching will not typically improve bandwidth. if the signal source has poor output return loss then it should be placed as close to the adc input pins as possible to reduce ripples in the frequency response caused by reflections at both the ADC12DJ3200QML-SP input pins and source output pins. 8.1.3 clocking the ADC12DJ3200QML-SP clock inputs must be ac-coupled to the device to provide rated performance. the clock source must have extremely low jitter (integrated phase noise) to achieve rated performance. recommended clock synthesizers include the lmx2615-sp , lmx2592 and lmx2582 . the jesd204b data converter system (adc plus fpga) requires additional sysref and device clocks. the lmk04832 , lmk04828 , and lmk04821 devices are an excellent choice to generate these clocks. depending on the adc clock frequency and jitter requirements, this device may also be used as the system clock synthesizer or as a device clock and sysref distribution device when multiple ADC12DJ3200QML-SP devices are used in a system. 8.1.4 radiation environment recommendations careful consideration should be given to the environmental conditions when using a product in a radiation environment. 8.1.4.1 single event latch-up (sel) one-time single event latch-up (sel) testing was performed according to eia/jedec standard, eia/jedec57. the linear energy transfer threshold (letth) shown in features is the maximum let tested. 8.1.4.2 single event functional interrupt (sefi) the register map of ADC12DJ3200QML-SP was designed to hold the programmed values during radiation events up to the maximum let used for sel testing. advance information
121 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 8.1.4.3 single event upset (seu) the high speed digital path of ADC12DJ3200QML-SP is susceptible to radiation events including the ddc block and jesd204b block. the following recommendations are provided to allow automatic recovery and to improve the recovery time caused by the jesd204b interface block of ADC12DJ3200QML-SP being upset. ? always use a continuous, periodic sysref in order to quickly recover internal clocks and counters. set the period to be long enough to limit spurious performance degradation caused by coupling, but short enough to recover within the system requirements. sysref will help both the transmitter (ADC12DJ3200QML-SP) and receiver (fpga or asic) recover after a seu. sysref sets an upper bound for the time the link takes to discover a frame or multi-frame misalignment. as a minimum requirement, sysref must be asserted when the receiver asserts the jesd204b sync signal. ? the receiver (fpga or asic) must perform frame and multiframe alignment monitoring. monitoring should include both looking for misplaced or missing end-of-frame and end-of-multiframe characters. misplaced characters are those that occur in the incorrect spot of a frame or multiframe, meaning not the last character of a frame or multiframe. missing characters are those that the receiver deems should be included at the end of a frame or multiframe based on the character replacement rules of jesd204b. when two or more misplaced or missing characters are found (without receiving any in the correct position), the link should be reestablished by asserting sync to restart the cgs and ilas processes. ? enable scrambling to make sure the alignment characters are generated with consistent probabilities independent of the adc data. not using scrambling could result in long recovery times after a shift in frame or multiframe alignment. ? make sure that the receiver frame-alignment state machine is implemented according to the jesd204b standard to make sure that the link supports reinitialization over the data interface. the frame should be re- aligned if the transmitter (ADC12DJ3200QML-SP) re-initializes the link by sending k28.5 characters without the receiver asserting the sync signal. ? additional robustness can be achieved in the 12-bit, ddc bypass jmodes by monitoring the four tail bits at the end of each frame. missing or misplaced tailbits can be treated the same a frame misalignment error. the accumulators of the numerically-controlled oscillators (ncos) used by the ddc block are also susceptible to upsets. an upset of the nco phase can be detected by using the nco upset alarm feature described in nco upset detection . after an upset has been detected, the nco must be reinitialized if phase synchronization between multiple ADC12DJ3200QML-SP devices is required. a more robust solution can be achieved if the nco frequency is chosen to be a harmonic of the sysref frequency (integer related to the sysref frequency) and nco synchronization using sysref (ac coupled) described in nco phase synchronization is used. this allows sysref to automatically reset the nco phase after an upset and automatically recovers the phase synchronization between multiple ADC12DJ3200QML-SP devices without having to resynchronize all ADC12DJ3200QML-SP devices in the system. this condition is met if f nco = n f sysref . advance information
122 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2 typical application a common use-case for ADC12DJ3200QML-SP is as the digitizer in a wideband rf sampling receiver. many applications, such as wideband satellite communications or synthetic aperture radar (sar), will fall into this same common configuration. in this case, dc coupling is not required and therefore a transformer or balun is used to interface the single-ended amplifier with the differential inputs of ADC12DJ3200QML-SP. figure 120. typical configuration for wideband rf sampling receiver 8.2.1 design requirements a wideband rf sampling receiver can be configured in a number of different modes. for instance, ADC12DJ3200QML-SP could operate in dual channel mode and sample in either the 1st, 2nd or 3rd nyquist zone. however, in this example assume that ADC12DJ3200QML-SP operates in single-channel mode at a sampling rate of 6.4 gsps and the 2nd nyquist zone is used. the input signals can then be between 3.2 ghz to 6.4 ghz, less anti-alias filtering margin, when running in single-channel mode at 6.4 gsps. the rf components are not addressed in detail here, but will instead be discussed in generalities in the rf input signal path section. table 149. wideband rf sampling receiver system requirements system requirement specification units sampling rate 6.4 gsps instantaneous signal bandwidth 2.5 ghz input signal center frequency 4.8 ghz adc interface jesd204b ? maximum serdes line rate 6.4 gbps advance information clocking subsystem user control logic fpga or asic up to 16 lanes jesd204b sync~ device clock sysref device clock sysref spi reference clock lmk04832 anti-alias bpf lna lna anti-alias bpf lna lna ddc adc a adc b jesd 204b jesd 204b ddc lmx2615-sp pll + vco pll + vco sysref ADC12DJ3200QML-SP
123 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2 detailed design procedure the component selection and ADC12DJ3200QML-SP configuration for the application described in design requirements is discussed is this section. the components of the wideband rf sampling receiver are given in table 150 along with the reason for the selection. table 150. wideband rf sampling receiver component selection component selection reason adc ADC12DJ3200QML-SP sampling rate requirement (6.4 gsps) and high input frequency makes ADC12DJ3200QML-SP a natural choice. sampling clock generation lmx2615-sp lmx2615-sp generates a high performing sampling clock due to low jitter (45 fs) and high output swing. the sysref features simplify multi-device synchronization. clock distribution lmk04832 support for 7 jesd204 adcs, dacs or logic devices (fpga or asic) and a number of operating modes such as single pll mode, dual pll mode or clock distribution mode. transformer/balun bal-0208smg small size, wide frequency coverage and good performance within required frequency band. the ADC12DJ3200QML-SP configuration and key parameters are given in table 151 . the calculations or sources for the various parameters are provided where applicable. table 151. ADC12DJ3200QML-SP configuration and key parameters parameter calculation setting or value units jmode ? 1 ? ddc mode from jmode selection n/a (dual-channel mode only) ? adc channels from jmode selection 1 ? analog input used ina provides best performance in single-channel mode ina ? total serdes lanes from jmode selection 16 lanes serdes line rate f linerate = f clk * r 6.4 gbps links from jmode selection 2 links l (per link) from jmode selection 8 lanes / link m (per link) from jmode selection 8 converters / link f from jmode selection 8 frames / lane s from jmode selection 5 samples / frame k ceil(17/f) k min(32, floor(1024/f)) 8 (others allowed) frames / multiframe clk frequency f clk = f s / 2 (for single-channel mode) 3.2 ghz sysref frequency f sysref = f linerate / (10 * f * k * n) 10 / n mhz total clock jitter t = sqrt( clk 2 + aj 2 ) 83 fs advance information
124 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.1 rf input signal path most rf sampling receivers will include a number of low-noise amplifiers (lnas) or gain blocks after the antenna to increase the signal level of the desired signal. the use of appropriate band-limiting filters after the lnas reduces receiver sensitivity loss due to a blocking signal by rejecting unwanted frequencies. the final amplifier, which will drive the ADC12DJ3200QML-SP through the transformer, must be selected to provide high linearity (imd3, sfdr) at the full-scale input power level of the ADC12DJ3200QML-SP plus the insertion loss of the transformer. the noise figure performance of the final driver amplifier is less important than linearity as long as sufficient gain is provided by the previous gain stages. the maximum output power must be less than the absolute maximum input power of the ADC12DJ3200QML-SP in case of overdrive conditions. if the amplifier is capable of driving an output power larger than the ADC12DJ3200QML-SP can tolerate then an external clamping or limiting circuit must be implemented to protect the ADC12DJ3200QML-SP input. overdrive conditions must be corrected quickly to prevent cumulative damage to the ADC12DJ3200QML-SP. 8.2.2.2 calculating values of ac-coupling capacitors ac-coupling capacitors are used in the input clk and jesd204b output data pairs. the capacitor values must be large enough to address the lowest frequency signals of interest, but not so large as to cause excessively long startup biasing times, or unwanted parasitic inductance. the minimum capacitor value can be calculated based on the lowest frequency signal that is transferred through the capacitor. given a 50- single-ended clock or data path impedance, good practice is to set the capacitor impedance to be < 1 at the lowest frequency of interest. this setting provides minimal impact on signal level at that frequency. for the clk path, the minimum-rated clock frequency is 800 mhz. therefore, the minimum capacitor value can be calculated from: (12) setting z c = 1 and rearranging gives: (13) therefore, a capacitance value of at least 199 pf is needed to provide the low-frequency response for the clk path. if the minimum clock frequency is higher than 800 mhz, this calculation can be revisited for that frequency. similar calculations can be done for the jesd204b output data capacitors based on the minimum frequency in that interface. capacitors must also be selected for good response at high frequencies (low inductance) and with dimensions that match the high-frequency signal traces they are connected to. capacitors of the 0201 size are frequently well suited to these applications. advance information ( ) c 1/ 2 800 mhz 1 = 1 pf 99 = p w ( ) l c c k z 1/ 2 c = p |
125 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3 initialization set up the device and jesd204 interface require a specific startup and alignment sequence. the general order of that sequence is listed in the following steps. 1. power-up or reset the device. 2. apply a stable device clk signal at the desired frequency. 3. program jesd_en = 0 to stop the jesd204b state machine and allow setting changes. 4. program cal_en = 0 to stop the calibration state machine and allow setting changes. 5. program the desired jmode. 6. program the desired km1 value. km1 = k ? 1. 7. program sync_sel as needed. choose syncse or timestamp differential inputs. 8. configure device calibration settings as desired. select foreground or background calibration modes and offset calibration as needed. 9. program cal_en = 1 to enable the calibration state machine. 10. enable overrange via ovr_en and adjust settings if desired. 11. enable continuous sysref generation at the sysref source. 12. verify that sysref meets setup and hold times relative to clk by either running automatic sysref calibration or using sysref windowing (see the sysref capture for multi-device synchronization and deterministic latency section for more information). 13. program jesd_en = 1 to re-start the jesd204b state machine and allow the link to restart. 14. the jesd204b interface operates in response to the applied sync signal from the receiver. 15. program cal_soft_trig = 0. 16. program cal_soft_trig = 1 to initiate a calibration. 9 power supply recommendations the device requires two different power-supply voltages. 1.9 v dc is required for the va19 power bus and 1.1 v dc is required for the va11 and vd11 power buses. the power-supply voltages must be low noise and provide the needed current to achieve rated device performance. there are two recommended power supply architectures: 1. step down from the system voltage using high-efficiency dc/dc switching converters followed by a second stage of low-noise regulation by a low drop-out linear regulator (ldo). the ldo provides switching noise reduction, reduces passive filtering requirements and improves voltage accuracy if placed locally at the adc. 2. directly step down from the system voltage to the final adc supply voltages using high-efficiency dc/dc switching converters. this approach provides the best efficiency, but care must be taken to make sure switching noise is minimized to prevent degraded adc performance. additional passive filtering is required for best performance and any lossy series components may reduce the actual voltage at the adc. ti webench ? power designer can be used to select and design the individual power supply elements needed: see the webench ? power designer . a recommended dc/dc switching regulator for the first stage is the tps50601a-sp , but other similar devices can be used as well. recommended ldos for the second stage include tps7h1101a-sp , tps7a4501-sp and other similar devices. for the switcher only approach, the ripple filter must be designed to provide sufficient filtering at the switching frequency of the dc-dc converter and it's harmonics. webench ? reports the switching frequency when used to design the supply. each application will have different tolerances for noise on the supply voltage so strict ripple requirements are not provided. figure 121 and figure 122 illustrate the two approaches. advance information
126 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated figure 121. ldo linear regulator example figure 122. dc/dc switching regulator example 9.1 power sequencing the voltage regulators must be sequenced using the power-good outputs and enable inputs to make sure that the vx11 regulator is enabled after the va19 supply is good. similarly, as soon as the va19 supply drops out of regulation on power-down, the vx11 regulator is disabled. the general requirement for the adc is that va19 vx11 during power-up, operation, and power-down. ti also recommends that va11 and vd11 are derived from a common 1.1-v regulator. this recommendation makes sure that all 1.1-v blocks are at the same voltage, and no sequencing problems exist between these supplies. also use ferrite bead filters to isolate any noise on the va11 and vd11 buses from affecting each other. + gnd dc/dc buck 5 v 12 v gnd gnd 1.9 v 10 f fb gnd 0.1 f 0.1 f va19 dc/dc buck 1.1 v 10 f fb gnd 0.1 f 0.1 f va11 10 f fb gnd 0.1 f vd11 power good gnd 10 f gnd 0.1 f fb gnd gnd fb gnd ripple filter local filtering local filtering local filtering and digital noise rejection ripple filter + gnd dc/dc buck 5 v 12 v gnd 2.2 v 10 f fb gnd 0.1 f 0.1 f va19 dc/dc buck 1.4 v 10 f fb gnd 0.1 f 0.1 f va11 10 f fb gnd 0.1 f vd11 gnd 10 f gnd 0.1 f local filtering local filtering local filtering and digital noise rejection ldo gnd 1.9 v ldo gnd 1.1 v power good gnd gnd advance information
127 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines there are many critical signals that require specific care during board design: 1. analog input signals 2. clk and sysref 3. jesd204b data outputs: 1. lower eight pairs operating at up to 12.8 gbit per second 2. upper eight pairs operating at up to 6.4 gbit per second 4. power connections 5. ground connections items 1, 2, and 3 must be routed for excellent signal quality at high frequencies. use the following general practices: 1. route using loosely coupled 100- differential traces. this routing minimizes impact of corners and length- matching serpentines on pair impedance. 2. provide adequate pair-to-pair spacing to minimize crosstalk. 3. provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. 4. use smoothly radiused corners. avoid 45- or 90-degree bends. 5. incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50- , single-ended impedance. 6. avoid routing traces near irregularities in the reference ground planes. irregularities include ground plane clearances associated with power and signal vias and through-hole component leads. 7. provide symmetrically located ground tie vias adjacent to any high-speed signal vias. 8. when high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. if layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs. in addition, ti recommends performing signal quality simulations of the critical signal traces before committing to fabrication. insertion loss, return loss, and time domain reflectometry (tdr) evaluations should be done. the power and ground connections for the device are also very important. these rules must be followed: 1. provide low-resistance connection paths to all power and ground pins. 2. use multiple power layers if necessary to access all pins. 3. avoid narrow isolated paths that increase connection resistance. 4. use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power planes. advance information
128 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example figure 123 to figure 125 provide examples of the critical traces routed on the device evaluation module (evm). figure 123. top layer routing: analog inputs, clk and sysref, da0-3, db0-3 advance information
129 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) figure 124. gnd1 cutouts to optimize impedance of component pads advance information
130 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) figure 125. bottom layer routing: additional clk routing, da4-7, db4-7 advance information
131 ADC12DJ3200QML-SP www.ti.com slvsdr2 ? november 2018 product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.1.2 development support ? webench ? power designer ? direct rf-sampling radar receiver for l-, s-, c-, and x-band using adc12dj3200 reference design ? multi-channel jesd204b 15 ghz clocking reference design for dso, radar and 5g wireless testers 11.2 documentation support 11.2.1 related documentation for related documentation see the following: ? texas instruments, jesd204b multi-device synchronization: breaking down the requirements technical brief ? texas instruments, lm95233 dual remote diode and local temperature sensor with smbus interface and trutherm ? technology data sheet ? texas instruments, lmx2594 15-ghz wideband pllatinum ? rf synthesizer with phase synchronization and jesd204b support data sheet ? texas instruments, lmx2592 high performance, wideband pllatinum ? rf synthesizer with integrated vco data sheet ? texas instruments, lmx2582 high performance, wideband pllatinum ? rf synthesizer with integrated vco data sheet ? texas instruments, lmk0482x ultra low-noise jesd204b compliant clock jitter cleaner with dual loop plls data sheet ? texas instruments, tps6208x 3-a step-down converter with hiccup short-circuit protection in 2 2 qfn package data sheet ? texas instruments, tps82130 17-v input 3-a step-down converter microsip ? module with integrated inductor data sheet ? texas instruments, tps6213x 3-v to17-v, 3-a step-down converter in 3x3 qfn package data sheet ? texas instruments, tps7a7200 2-a, fast-transient, low-dropout voltage regulator data sheet ? texas instruments, tps74401 3.0-a, ultra-ldo with programmable soft-start data sheet ? texas instruments, adc12dj2700 evaluation module user ' s guide 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. advance information
132 ADC12DJ3200QML-SP slvsdr2 ? november 2018 www.ti.com product folder links: ADC12DJ3200QML-SP submit documentation feedback copyright ? 2018, texas instruments incorporated 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 9-nov-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 5962f1820901vxc preview clga zmx 196 119 tbd call ti call ti -55 to 125 adc12dj3200zmx/em preview clga zmx 196 119 tbd call ti call ti 25 to 25 padc12dj32zmx/em20 active clga zmx 196 1 tbd call ti call ti 25 to 25 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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